Y. Nagahisa

Bio: Y. Nagahisa is an academic researcher from Mitsubishi Electric. The author has contributed to research in topics: Schottky barrier & Schottky diode. The author has an hindex of 1, co-authored 1 publications receiving 32 citations.

Demonstration of SiC-MOSFET embedding Schottky barrier diode for inactivation of parasitic body diode

Abstract: External Schottky barrier diodes (SBD) are generally used to suppress the conduction of the body diode of MOSFET. A large external SBD is required for a high voltage module because of its high specific resistance, while the forward voltage of SBD should be kept smaller than the built-in potential of the body diode. Embedding SBD into MOSFET with short cycle length increases maximum source-drain voltage where body diode remains inactive, resulting in high current density of SBD current. We propose a MOSFET structure where an SBD is embedded into each unit cell and an additional doping is applied, which allows high current density in reverse operation without any activation of body diode. The proposed MOSFET was successfully fabricated and much higher reverse current density was demonstrated compared to the external SBD. We can expect to reduce total chip size of high voltage modules using the proposed MOSFET embedding SBD.

Monolithically Integrated 4H-SiC MOSFET and JBS Diode (JBSFET) Using a Single Ohmic/Schottky Process Scheme

Abstract: This letter reports a new 900 V 4H-SiC JBSFET containing an MOSFET with an integrated JBS diode in the center area of the chip. Both MOSFET and JBS diode structures utilize the same edge termination structure,which results in 30% reduction in SiC wafer area consumption in case of 10 A rating device. In order to form a Schottky contact for the JBS diode as well as ohmic contacts for n+ source and p+ body of the MOSFET,a simple metal process flow has been newly developed. It was found that Ni can simultaneously form ohmic contacts on n+ and p+ implanted regions while it remains a Schottky contact on the n-epitaxial drift layer when it is annealed at moderate temperature (900°C for 2 min). The proposed JBSFET was successfully fabricated using a nine-mask on 6-in 4H-SiC wafers.

6.5 kV schottky-barrier-diode-embedded SiC-MOSFET for compact full-unipolar module

Abstract: For higher-voltage SiC modules, larger SBD chips are required as free-wheel diodes to suppress current conduction of the body diodes of MOSFETs, which causes bipolar degradation following the expansion of stacking faults. By embedding an SBD into each unit cell of a 6.5 kV SiC-MOSFET, we achieved, without using external SBDs, a high-voltage switching device that is free from bipolar degradation. Expansion of the active area by embedding SBDs is only 10% or less, whereas the active area of external SBDs can be over three times larger than that of the coupled MOSFET. The fabricated 6.5 kV SBD-embedded SiC-MOSFETs show sufficiently high breakdown voltages, low specific on-resistances, no bipolar degradation, and good reliability.

High efficiency high reliability SiC MOSFET with monolithically integrated Schottky rectifier

Abstract: A junction barrier controlled Schottky rectifier integrated silicon carbide MOSFET (SiC JMOS) is proposed in this paper, which merged a double implanted MOSFET (DMOS) and junction barrier controlled Schottky diode (JBS) in a monolithic SiC device without any additional process and area penalty. JMOS device in this work exhibits a lower reverse conduction voltage drop than conventional SiC DMOS. There is a 47% improvement on V SD . There's also superior in dynamic performances such like lower reverse recovery charge (Qrr) and maximum reverse recovery current (IRMax) due to characteristics of unipolar devices. As a result, JMOS is 54% lower in Q rr and 40% lower in I RMax . The integrated JBS could also prevent the potential failure caused by the transformation of dislocation defects into stacking faults due to the recombination of injected minority carriers when parasitic body diode in SiC MOSFET was turned on. In this work, we make characteristics comparison and build a testing platform to verify the efficiency and reliability improvement of SiC JMOS from conventional SiC DMOS. The experiment result shows that we could gain better system performance and reliability with less cost and higher power density.

Body PiN diode inactivation with low on-resistance achieved by a 1.2 kV-class 4H-SiC SWITCH-MOS

Abstract: Integration of SBD into SiC-MOSFET is promising to solve body-PiN-diode related problems known such as forward degradation and reverse recovery loss Particularly in lower breakdown-voltage-class SBD-integrated MOSFET, cell pitch reduction has a greater impact on inactivating the body-PiN-diode Here, we developed a novel device called an SBD-wall-integrated trench MOSFET (SWITCH-MOS), in which small cell pitch of 5pm was realized by utilizing trench side walls both for SBD and MOS channel with buried p+ layer The fabricated 12 kV SWITCH-MOS successfully suppressed the forward degradation under extremely high current density condition with low switching loss, low specific on-resistance, and low leakage current

Investigation on Degradation of SiC MOSFET Under Surge Current Stress of Body Diode

Abstract: Eliminating antiparallel silicon carbide Schottky barrier diode (SiC SBD) and making use of the intrinsic body diode of SiC metal–oxide–semiconductor-field-effect transistor (SiC MOSFET) offer a cost-effectiveness solution without obviously sacrificing the conversion efficiency in some power converter applications. Although the body diode of commercial SiC MOSFET has been qualified by several manufacturers, the reliability of SiC MOSFET under repetitive surge current stress of body diode has not been sufficiently studied. In this article, the new degradation phenomena of SiC MOSFET’s gate oxide are observed, and the degradation mechanism is discussed when the intrinsic body diode of the 1200-V SiC planar gate MOSFETs was subjected to surge current stress. TCAD simulation and experimental measurements indicate that the generation and accumulation of electrons or holes within the gate oxide under surge current stress are the main reasons for the degradation of SiC MOSFET. Finally, a mitigation technique with optimal gate turn-off voltage is suggested to suppress the gate oxide degradation of the SiC MOSFET under surge current stress of its body diode.