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Y. Sato

Bio: Y. Sato is an academic researcher from Tohoku University. The author has contributed to research in topics: Thermal copper pillar bump & Chip. The author has an hindex of 3, co-authored 7 publications receiving 22 citations.

Papers
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Proceedings ArticleDOI
Y. Sato1, Hideo Miura1
01 Jan 2005
TL;DR: In this paper, a new nondestructive evaluation method of adhesion condition between a Si chip and small metallic bumps in a flip chip bonding structure is proposed, where the local deformation of a surface of an LSI chip mounted on a substrate is measured using a scanning blue laser microscope.
Abstract: A new nondestructive evaluation method of adhesion condition between a Si chip and small metallic bumps in a flip chip bonding structure is proposed The local deformation of a surface of a Si chip mounted on a substrate increases drastically between two bumps with decrease of the thickness of the chip thinner than 200 μm The magnitude of the local deformation exceeds 100 nm easily Once the lack or delamination of the metallic bumps occurs at the interface, the local deformation at a surface of a Si chip around the bump changes remarkably The change of the magnitude of the local deformation reaches about 50 nm to 600 nm depending on the thickness of the chip Such a small change of deformation can be measured using a scanning blue laser microscope Therefore, the adhesion condition of the area-arrayed bumps can be examined by measuring the local deformation of a surface of an LSI chip mounted on a substrateCopyright © 2005 by ASME

8 citations

Proceedings ArticleDOI
19 May 2014
TL;DR: In this paper, the authors optimized edge-trimming and back-grinding followed by chemical-mechanical polishing processes for wafer-to-wafer integration of 12-inch LSI wafer with thickness ≤ 50 μm.
Abstract: Thinning down large scale integrated-chip (LSI) wafers to below 50 μm thickness is inevitable for the wafer-to-wafer (WtW) process as well as chip-to-wafer (CtW) or chip-to-chip (CtC) processes in three-dimensional LSI integration. In this work we have optimized edge-trimming and back-grinding followed by chemical-mechanical polishing processes for WtW integration of 12-inch LSI wafer with thickness ≤ 50 μm. After optimization, we were able to achieve the total thickness variation (TTV) of less than 200 nm in the 50 μm-thick LSI wafers. Also, it was found that the smaller TTV value of temporarily bonded wafer before wafer thinning greatly helps to reduce the TTV in the back-ground and polished wafers. We successfully integrated 50 μm-thick 8- and 12-inch LSI wafers to their respective passive interposers using Cu-TSVs, and the electrical properties of TSVs were evaluated.

5 citations

Proceedings ArticleDOI
27 May 2014
TL;DR: A 3D stacked multicore processor with TSV self-test and self-repair functions for highly area-efficient TSV repair has been proposed in this article, which is implemented using die-level 3D integration and backside TSV technologies.
Abstract: A highly dependable 3-D stacked multicore processor with TSV self-test and self-repair functions for highly area-efficient TSV repair has been proposed. The prototype 3-D stacked multicore processor with two layer structure is implemented using die-level 3-D integration and backside Cu TSV technologies. The basic functions of tier boundary scan and self-repair circuits via TSVs between each layer in the 3-D stacked multicore processor are successfully evaluated. X-ray computed tomography (X-ray CT) scanning technology is proposed as a nondestructive failure analysis method to characterize high-density TSVs integration, and bump joining qualities in the 3-D stacked multicore processor.

5 citations

Proceedings ArticleDOI
26 May 2015
TL;DR: In this article, the effect of post-heat treatment of chemical-vapor-deposited polyimide (PI) liner along the Cu-TSV side-wall in the 3D-LSI chips was investigated for leakage current, parasitic capacitance and thermal stability.
Abstract: The effect of post-heat treatment of chemical-vapor-deposited polyimide (PI) liner along the Cu-TSV side-wall in the 3D-LSI chips was investigated for leakage current, parasitic capacitance and thermal stability by analyzing current-voltage (I–V), capacitance-voltage (C-V), and x-ray photo-electron spectroscopy (XPS) data. From the I–V data it is inferred that the post heat treatment of 250 nm-thick PI at 200 °C has tremendously suppressed the leak current as compared to the leak current in the pristine PI film. In the case of annealed PI the leak current was minimized to nearly half for the stress voltage of up to ±20 V, whereas it was reduced by nearly three (3) orders for the stress value of ±40 V. The post annealing process also suppresses the hysteresis, and this effect is pronounced for the thicker film.

4 citations

Proceedings ArticleDOI
01 Dec 2014
TL;DR: In this paper, a 3D stacked multicore processor module composed of 4-layer stacked 3D multicore processors and 2-layer stack 3D cache memory chip is implemented using reconfigured multichip-on-wafer 3D integration and backside TSV technologies for the first time.
Abstract: A highly dependable 3-D stacked multicore processor module composed of 4-layer stacked 3-D multicore processor chip and 2-layer stacked 3-D cache memory chip is implemented using reconfigured multichip-on-wafer 3-D integration and backside TSV technologies for the first time. Tier boundary scan, self-repair circuits, and BIST circuits in the 4-layer stacked 3-D multicore processor chip and the basic read/write functions of memory circuits in the 2-layer stacked 3-D cache memory chip are successfully evaluated. High-density TSVs and micro-joining characteristics in the 3-D stacked chip were evaluated by a non-destructive method using high resolution X-ray CT scanning tool.

3 citations


Cited by
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Proceedings ArticleDOI
27 May 2014
TL;DR: In this paper, the potential of x-ray micro-computed tomography (μCT) to fulfill the need for non-destructive three dimensional imaging of electronic assemblies has been evaluated.
Abstract: The industry is going through a transition in material sets for second level interconnects including adoption of leadfree solders. High-rel systems may often have a mix of components with different solder alloys in the printed circuit assemblies including both leaded and leadfree solders because some original leaded components may only be available in leadfree configurations. In this paper, the potential of x-ray micro-computed tomography (μCT) to fulfill the need for non-destructive three dimensional imaging of electronic assemblies has been evaluated. A number of defect seeded assemblies have been used for detection of a number of common solder interconnect defects and failure modes. In addition, the ability of the x-ray μCT for examination of complete products has been examined. Three-dimensional rendered versions of the board assemblies have been constructed for visualization of the defects and failure modes. Void sizes have been measured using Volume Graphics reconstruction and Matlab modules. In each case, the assemblies have been cross-sectioned after imaging by x-ray μCT to ascertain the morphology of the defect or failure mode using optical imaging. Results indicate that x-ray μCT is capable of providing high resolution imaging of the common defect types and failure modes in electronic assemblies and has potential for risk mitigation in sustainment of long-life high-rel systems.

20 citations

Journal ArticleDOI
TL;DR: In this article, the phase growth process of solder microjoints was determined by observing the computed tomography (CT) images obtained consecutively at the fixed point of the target joining, and the distribution of constituent phases in the Sn-Pb eutectic solder was identified based on the estimation value of the X-ray linear attenuation coefficient.
Abstract: In high-density packaging technology, one of the most important issues is the reliability of the microjoints connecting large scale integrated circuit chips to printed circuit boards electrically and mechanically. The development of nondestructive testing methods with high spatial resolution is expected to enhance reliability. An X-ray microtomography system called SP-μCT has been developed in Super Photon ring-8 GeV (SPring-8), the largest synchrotron radiation facility in Japan. In this work, SP-μCT was applied in the nondestructive evaluation of microstructure evolution, that is, the phase growth due to thermal cyclic loading in solder ball microjoints. Simulating solder microjoints used in a flip chip, specimens were fabricated by joining a Sn-Pb eutectic solder ball 100 μm in diameter to a steel pin in the usual reflow soldering process. The phase growth process was determined by observing the computed tomography (CT) images obtained consecutively at the fixed point of the target joining. In the reconstructed CT images, the distribution of the constituent phases in the Sn-Pb eutectic solder was identified based on the estimation value of the X-ray linear attenuation coefficient. Consequently, the microstructure images obtained nondestructively by SP-μCT provided us with the following useful information for evaluating the reliability of the solder microjoints. First, each phase involves not dispersing particles but a three-dimensional monolithic structure like a sponge. Second, the phase growth proceeds in such a way that the average phase size to the fourth power increases proportionally to the number of cycles. Finally, in the vicinity of the joining interface, more rapid phase growth occurs compared to the other regions because local thermal strain due to the mismatch of thermal expansion leads to a remarkable phase growth.

15 citations

Journal ArticleDOI
TL;DR: In this article , a novel thinning method was proposed that sequentially used constant-pressure diamond grinding and fixed-abrasive CMP to thin a wafer, which could provide an ultra-smooth surface with a roughness less than Ra 2 nm while the processing stress was no more than 150 MPa.

12 citations

Journal ArticleDOI
TL;DR: In this article, a novel thinning method was proposed that sequentially used constant-pressure diamond grinding and fixed-abrasive CMP to thin a wafer, which could provide an ultra-smooth surface with a roughness less than Ra 2'nm while the processing stress was no more than 150'MPa, making it ideal for the removal of grinding damage layers.

12 citations