Yabin Wang

Bio: Yabin Wang is an academic researcher from Fudan University. The author has contributed to research in topics: Field-programmable gate array & Programmable Array Logic. The author has an hindex of 1, co-authored 2 publications receiving 6 citations.

An FPGA configuration circuit used for fast and partial configuration

Abstract: An improved architecture used for FPGA's fast and partial configuration is proposed. It is designed based on a 32 bits wide data bus, which can be controlled by a set of instructions. A partial control register and an address decoding logic are added in this design. Multiple configuration interfaces could be connected in this architecture, making hardware updating fast and convenient. Comparing with Virtex Series FPGA's configuration architecture, produced by Xilinx Corp., which only can configure memory cells by frame, this new architecture could configure any single memory cell in FPGA, offering more flexible configuration operations.

The Architecture of FDP FPGA Device

Abstract: A novel FuDan programmable(FDP) FPGA device architecture was presented. The new 3-LUT based logic cell could increase logic density about 11% comparing with a traditional 4-input LUT. The uniquely hierarchy programmable routing fabrics and effective switch box could optimize the routing wire segments and make it possible for different length to connect directly and efficiently. The FDP FPGA device contains 1,600 programmable logic cells, 160 programmable IO Blocks and 16 K bits dual port block RAM IP Core. It was fabricated with SMIC 0.18 mum Logic 1P6M Salicide 1.8 V/3.3 V process, its die size is 6.1times6.6 mm2, with the package of QFP208.

Design and implementation of the configuration circuit for FDP FPGA

Abstract: This paper presents a configuration circuit used in the FDP (FDP: Fu Dan Programmable device) FPGA chip. This circuit could write configuration data into FDP and read back data from FDP successfully. Comparing with Xilinx Virtex Series FPGA chips, the smallest configuration section of which is one data-frame, the proposed circuit could write each single memory cell in FDP, providing more flexible configuration operations. A standard configuration interface, Serial Peripheral Interface (SPI), is added in this circuit to replace using the expensive Xilinx Platform configuration Flash PROMs. A group of high precise sensitive amplifiers is adopted in this configuration circuit, which are used to magnify the read back data values. Through a novel write/read asynchronous FIFO structure in FDP, which divides the external interface and internal configuration circuit into two clock domains, designers could set the external clock and internal clock separately. Basic functions of the configuration circuit have been correctly verified by Altera DE2 development board platform. The post layout simulation results indicate via this configuration circuit, each data frame in FDP could be written in 4 mus, and could be read back in 5 mus. The total configuration time of FDP chip is about 6.5 ms.

A SPI FLASH-based FPGA dynamic reconfiguration method

Abstract: To make the FPGA configuration more flexible and easier, this article designs a SPI FLASH-based FPGA dynamic reconfiguration method according to the principle of FPGA configuration. In the paper, some of the key technologies in software design are analyzed and solved. Besides, the design has been verified on the hardware platform as well. The results show that this design is reasonably practicable and has achieved the design requirements of dynamic reconfiguration.

Fast configuration architecture of FPGA suitable for bitstream compression

Abstract: In this paper, fast configuration architecture of FPGA suitable for bitstream compression is proposed and implemented for FDP2009-II-SOPC (FDP2009-II-SOPC: Fudan Programmable device 2009-II-SOPC) FPGA with SMIC 0.13 CMOS process. This circuit features an addressable configuration register and the internal frame decoder that makes a 32-bit memory cell of FPGA addressable. The improved configuration circuit which can configuration every 32bit memory cells could provide faster configuration speed and more flexible partial configuration operations. The die size of FDP2009-II-SOPC is about 6.3mm*4.5mm=28.35mm2 and the area of this configuration circuit is about 1.7mm2. The post layout simulation shows that this fast configuration circuit of FDP2009-II-SOPC FPGA could work correctly and efficiently and the configuration time is less than 53% of that of Xilinx VirtexII series FPGA1.

JTAG-based bitstream compression for FPGA configuration

Abstract: A novel circuit architecture for configuration bitstream compression based on JTAG is proposed. The circuit decompresses and compresses bitstream while FPGA is configured and performs readback accordingly. The compression and decompression operations are implemented dynamically by a concise hardware architecture within the framework of IEEE standard 1149.1. Run Length Encode/Decode (RLE/D) algorithm is used for compression coding. Using Chartered 0.13um single-poly-8-metal process, the chip size is 0.01 mm2.

An FPGA configuration circuit based on JTAG

Abstract: An FPGA configuration circuit based on JTAG is designed. The configuration circuit has the JTAG architecture which is compatible with the IEEE standard 1149.1. Under the shift function of JTAG, a data chain for configuration is provided. The process of the configuration is controlled by three simple counters. Implemented with the CSMC 0.5um technology, the configuration circuit has the area of 1.404mm2, occupies the 3 percent of total FPGA area. Compared with the control scheme of complex state machine, this design is simple and has been used in an FPGA.