Yan-Juan Liu

Bio: Yan-Juan Liu is an academic researcher from Harbin Engineering University. The author has contributed to research in topics: Trench & Bipolar junction transistor. The author has an hindex of 5, co-authored 10 publications receiving 71 citations.

An Optimized Structure of 4H-SiC U-Shaped Trench Gate MOSFET

Abstract: In this paper, an optimized structure of 4H-SiC U-shaped trench gate MOSFET (UMOSFET) with low resistance is proposed. The optimized structure adds an n-type region, wrapping the p+ shielding region incorporated at the bottom of the trench gate. The depletion region formed by the p+ shielding region reduces greatly for the high dopant concentration of the added region. This added region also conducts electrons downward and expands the electrons to the bottom of the p+ shielding region. We discussed the influence of dopant concentration and the width of the added region on the breakdown voltage (BV) and the ON-resistance in this paper. A reasonable size and an optimized concentration were chosen for the added region in our simulation. The channel inversion layer mobility was set to 50 cm $^{2}$ /Vs, and the specific ON-resistance and the BV were 1.64 $\text{m}\Omega \cdot {\rm cm}^{2}$ ( $V_{\mathrm {GS}}= 15$ V, $V_{\mathrm {DS}}= 1$ V, and no substrate resistance was included) and 891 V, respectively, using the numerical simulation.

4H-SiC Trench IGBT With Back-Side n-p-n Collector for Low Turn-OFF Loss

Abstract: In this paper, an n-p-n collector incorporated in the back side of a 4H-SiC trench IGBT is presented to reduce the turn-off energy loss. A comparative study between the proposed structure and the conventional structure is conducted through ATLAS. The simulation results have demonstrated that the turn-off energy loss is reduced by more than 82.96% with a slight degradation in the on-state voltage drop.

High-Performance Split-Gate-Enhanced UMOSFET With Dual Channels

Abstract: This paper presents an optimized split-gate-enhanced trench MOSFET with dual channels (DSGE-UMOS). The 2-D device simulator ATLAS is used to investigate the characteristics of the proposed structure. When compared with the conventional SGE-UMOS, the optimized device shows a significant reduction in the specific on-resistance ( ${R}_{ {\mathrm{\scriptscriptstyle ON}}\text {-sp}}$ ) at a breakdown voltage of 120 V, which is due to the adoption of an additional p-type well region. Furthermore, the proposed structure can also enhance the single-event burnout (SEB) survivability. Based on the DSGE-UMOS, the hardened DSGE-UMOS (an n-type buffer layer is added between the epitaxial layer and substrate layer) is also investigated that the addition of the buffer layer can improve the SEB performance a lot.

A Novel Trench-Gated Power MOSFET With Reduced Gate Charge

Abstract: In this letter, we propose a novel trench power MOSFET structure with a p-n junction in trench to reduce the gate charge We utilize the 2-D device simulator, ATLAS, to investigate the characteristics of the proposed structure and compare with the conventional structure As a result, the proposed structure exhibits 495% enhancement in gate-charge $Q_{\mathrm {\mathbf {g}}}$ as compared with the conventional structure, without degrading the other electrical characteristics

A Low Turn-Off Loss 4H-SiC Trench IGBT With Schottky Contact in the Collector Side

Abstract: In this paper, a 4H-SiC trench insulated gate bipolar transistor (IGBT) incorporating a Schottky contact in the collector side is proposed to reduce the turn-off energy loss. The proposed structure is explored and compared with the conventional IGBT using ATLAS. The simulation results have indicated that the reduction in turn-off energy loss is more than 88%, with a slight degradation in the ${I}$ – ${V}$ characteristics. Concurrently, with the same on-state voltage drop, the turn-off loss is reduced by a figure of 84%.

Power Semiconductor Devices for Smart Grid and Renewable Energy Systems

Abstract: Modern civilization is related to the increased use of electric energy for industry production, human mobility, and comfortable living. Highly efficient and reliable power electronic systems, which convert and process electric energy from one form to the other, are critical for smart grid and renewable energy systems. The power semiconductor device, as the cornerstone technology in a power electronics system, plays a pivotal role in determining the system efficiency, size, and cost. Starting from the invention and commercialization of silicon bipolar junction transistor 60 years ago, a whole array of silicon power semiconductor devices have been developed and commercialized. These devices enable power electronics systems to reach ultrahigh efficiency and high-power capacity needed for various smart grid and renewable energy system applications such as photovoltaic (PV), wind, energy storage, electric vehicle (EV), flexible ac transmission system (FACTS), and high voltage dc (HVDC) transmission. In the last two decades, newer generations of power semiconductor devices based on wide bandgap (WBG) materials, such as SiC and GaN, were developed and commercialized further pushing the boundary of power semiconductor devices to higher voltages, higher frequencies, and higher temperatures. This paper reviews some of the major power semiconductor devices technologies and their potential impacts and roadmaps.

A Review of SiC IGBT: Models, Fabrications, Characteristics, and Applications

Abstract: Along with the increasing maturity for the material and process of the wide bandgap semiconductor silicon carbide (SiC), the insulated gate bipolar transistor (IGBT) representing the top level of power devices could be fabricated by SiC successfully This article presents a thorough review of development of SiC IGBT in the past 30 years The progresses of models, structure design, and performance in SiC IGBT are summarized The challenges resulting from fabrication process and switching characteristics are discussed and analyzed in detail The experimental results and existing problems in SiC IGBT-based applications are summarized in the end

Power semiconductor devices for smart grid and renewable energy systems

Abstract: This chapter intends to provide a comprehensive and comparative discussion of various important power device technologies which are critical for industrial, smart grid and renewable energy applications. A power semiconductor switch is a three‐terminal device that can either conduct a current when it is commanded ON, or block a voltage when it is commanded OFF through the control terminal. Modern power converters require the power device to switch at high frequencies. A modern power semiconductor device operates between ON and OFF states at a high switching frequency. One way to compare state‐of‐the‐art power devices, especially their commercial readiness, is to compare their absolute voltage and current ratings. The chapter reviews several important innovations in Si power devices. The most exciting development in power semiconductor devices in the last decade is the commercialization of a number of wide bandgap power devices.

4H-SiC Trench MOSFET With Floating/Grounded Junction Barrier-controlled Gate Structure

Abstract: A novel silicon carbide (SiC) trench MOSFET with floating/grounded junction barrier-controlled gate structure (FJB-MOS/GJB-MOS) is presented and investigated utilizing Sentaurus TCAD simulations. The split P+ region introduced beneath the trench could better shield the gate oxide from the high electric field in the blocking mode, leading to an enhancement in the breakdown voltage while without significant degradation of other characteristics. As a result, the FJB-MOS with floating P+ shielding exhibits a higher figure of merit related to the breakdown voltage and the specific on-resistance ( ${V}_{\textsf {BR}}^{{\,\textsf {2}}}/{R}_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}$ ), which is improved by 15% and 49%, respectively, with comparison to those of the state-of-the-art double-trench MOSFET and L-shaped gate trench MOSFET. In terms of the GJB-MOS with grounded P+ shielding, it shows great advantage in reducing the switching losses thanks to the lower specific gate–drain charge ${Q}_{{\:\textsf {gd,sp}}}$ and is more conductive to high frequency applications. Additionally, the formation of the P+ region is aided by the Sentaurus Process and the processing implementation of the proposed structure is discussed.

Optimization of SiC UMOSFET Structure for Improvement of Breakdown Voltage and ON-Resistance

Abstract: This paper proposes an optimized structure of 4H-SiC U-shaped accumulation-mode MOSFET (U-ACCUFET), which exhibits lower on-resistance and higher breakdown voltage. In this structure, an n-doped region is added underneath the gate trench, which covers the p+ shielding region. The new appended section spreads out the electrons to the bottom of the p+ shielding region and conducts the electrons in the downward direction. Output on-state characteristic curves ( ${I}_{\mathrm {DS}}$ – ${V}_{\textsf {DS}}$ ), on-resistance, transfer characteristic curves ( ${I}_{\textsf {DS}}$ – ${V}_{\textsf {GS}}$ ), threshold voltage ( ${V}_{t}$ ), subthreshold slope, and off-state characteristics of the optimized structure are observed. The proposed device shows on-resistance of 1.55 $\text{m}\Omega ~\cdot $ cm2 at ${V}_{\textsf {GS}}= \textsf {16}$ V and ${V}_{\textsf {DS}}= \textsf {1}$ V and breakdown voltage of 2624 V at ${V}_{\textsf {GS}}= \textsf {0}$ V. The simulation results indicate a superior performance of the optimized U-ACCUFET structure as the on-resistance reduces by 6% and breakdown voltage increases by 7.2% as compared with that of the conventional one. Also, the figure of merit ${V}_{\textsf {BR}}^{\textsf {2}}/{R}_{ \mathrm{\scriptscriptstyle ON}}$ is improved by 21.6%.