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Author

Yang Xu

Bio: Yang Xu is an academic researcher from Delft University of Technology. The author has contributed to research in topics: Image sensor & Progressive scan. The author has an hindex of 3, co-authored 5 publications receiving 113 citations.

Papers
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Proceedings ArticleDOI
03 Apr 2012
TL;DR: By implementing a high-gain column-level amplifier and CMS technique together with an in-pixel buried-channel source follower (BSF) [6], the TRN level can be reduced even further.
Abstract: For low-light-level imaging, the performance of a CMOS image sensor (CIS) is usually limited by the temporal readout noise (TRN) generated from its analog readout circuit chain. Although a sub-electron TRN level can be achieved with a high-gain pixel-level amplifier, the pixel uniformity is highly impaired up to a few percent by its open-loop amplifier structure [1]. The TRN can be suppressed without this penalty by employing either a high-gain column-level amplifier [2] or a correlated multiple sampling (CMS) technique [3–5]. However, only 1-to-2 electron TRN level has been reported with the individual use of these approaches [2–5], and the low-frequency noise of the in-pixel source follower i.e. 1/fand RTS noise is a further limitation. Therefore, by implementing a high-gain column-level amplifier and CMS technique together with an in-pixel buried-channel source follower (BSF) [6], the TRN level can be reduced even further.

73 citations

Journal ArticleDOI
TL;DR: In this article, a low-noise CMOS image sensor using column-parallel high-gain signal readout and digital correlated multiple sampling (CMS) is presented.
Abstract: This paper presents a low-noise CMOS image sensor using column-parallel high-gain signal readout and digital correlated multiple sampling (CMS). The sensor used is a conventional 4T active pixel with a pinned-photodiode as detector. The test sensor has been fabricated in a 0.18 μm CMOS image sensor process from TSMC. The random noise from the pixel readout chain is reduced in two stages, first using a high gain column parallel amplifier and second by using the digital CMS technique. The dark random noise measurement results show that the proposed column-parallel circuits with digital CMS technique is able to achieve 127 μVrms input referred noise. The significant reduction in the sensor read noise enhances the sensor's signal-to-noise ratio (SNR) with 10.4 dB. Such sensors are very attractive for low-light imaging applications which demand high SNR values.

44 citations

Journal ArticleDOI
TL;DR: In this article, a method to characterize the transfer gate (TG)-related parameters in a 4 T pixel was presented, which is based on the pinning voltage measurement, which was proposed by Tan et al. Using this method, the TG ON and OFF surface potential can be characterized.
Abstract: A method to characterize the transfer gate (TG)- related parameters in a 4 T pixel is presented. The method is based on the pinning voltage measurement, which is proposed by Tan et al. [1] Using this method, the TG ON and OFF surface potential can be characterized. Based on the TG ON potential characterization, and according to the MOSFET model, the TG channel doping and the oxide thickness can be extracted from the measurements. Based on the TG OFF potential characterization, the TG surface potential dependence on the TG design parameters and the pixel biasing condition are analyzed. Using this method, whether the device is suffering from the drain-introduced barrier lowering effect or the short channel effect can be easily determined.

8 citations

Journal ArticleDOI
TL;DR: This paper presents the first CMOS image sensor which implements a charge domain interlacing principle to improve the signal-to-noise ratio (SNR) under equal exposure condition (integration time and light intensity).
Abstract: This paper presents the first CMOS image sensor which implements a charge domain interlacing principle to improve the signal-to-noise ratio (SNR) under equal exposure condition (integration time and light intensity). Inspired by the shared amplifier pixel structure, a novel pixel is designed to fit the charge domain interlacing principle, which works in field integration and frame integration mode. The designed image sensor is implemented in TSMC 0.18 μm CIS technology. This CMOS image sensor also contains a programmable universal image sensor peripheral circuit, allowing this sensor also to support normal progressive scan. By comparing the performances of the sensor working in charge domain interlacing and in the progressive scan, the chip measurement results prove that under the same exposure condition, the light response of the charge domain interlacing is twice that of the progressive scan. The SNR performance can be increased by 6 dB in low light level conditions.

3 citations

Proceedings ArticleDOI
01 Nov 2010
TL;DR: This paper presents the first CMOS image sensor which implements a charge domain interlacing principle to improve the signal-to-noise ratio (SNR) under the same exposure condition (integration time and light intensity).
Abstract: This paper presents the first CMOS image sensor which implements a charge domain interlacing principle to improve the signal-to-noise ratio (SNR) under the same exposure condition (integration time and light intensity). A novel pixel is designed to fit the charge domain interlacing principle, which works in field integration and frame integration mode. This CMOS image sensor also contains a programmable universal image sensor peripheral circuit, thus this sensor can also be used in progressive scan. Comparing the performances of the sensor working in charge domain interlacing and in the progressive scan, the chip measurement results prove that under the same exposure condition, the light response of the charge domain interlacing is the twice that of the progressive scan. The SNR performance can be increased by 6 dB in low light level.

2 citations


Cited by
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Journal ArticleDOI
TL;DR: In this paper, a CMOS single-photon avalanche diode (SPAD)-based quarter video graphics array image sensor with 8- $\mu \text{m}$ pixel pitch and 26.8% fill factor was presented.
Abstract: A CMOS single-photon avalanche diode (SPAD)-based quarter video graphics array image sensor with 8- $\mu \text{m}$ pixel pitch and 26.8% fill factor (FF) is presented. The combination of analog pixel electronics and scalable shared-well SPAD devices facilitates high-resolution, high-FF SPAD imaging arrays exhibiting photon shot-noise-limited statistics. The SPAD has 47 counts/s dark count rate at 1.5 V excess bias (EB), 39.5% photon detection probability (PDP) at 480 nm, and a minimum of 1.1 ns dead time at 1 V EB. Analog single-photon counting imaging is demonstrated with maximum 14.2-mV/SPAD event sensitivity and 0.06e− minimum equivalent read noise. Binary quanta image sensor (QIS) 16-kframes/s real-time oversampling is shown, verifying single-photon QIS theory with $4.6\times $ overexposure latitude and 0.168e− read noise.

108 citations

Journal ArticleDOI
Eric R. Fossum1, Jiaju Ma1, Saleh Masoodian1, Leo Anzagira1, Rachel Zizza1 
10 Aug 2016-Sensors
TL;DR: The Quanta Image Sensor (QIS) concept and its imaging characteristics are reviewed, which represents a possible major paradigm shift in image capture.
Abstract: The Quanta Image Sensor (QIS) was conceived when contemplating shrinking pixel sizes and storage capacities, and the steady increase in digital processing power. In the single-bit QIS, the output of each field is a binary bit plane, where each bit represents the presence or absence of at least one photoelectron in a photodetector. A series of bit planes is generated through high-speed readout, and a kernel or “cubicle” of bits (x, y, t) is used to create a single output image pixel. The size of the cubicle can be adjusted post-acquisition to optimize image quality. The specialized sub-diffraction-limit photodetectors in the QIS are referred to as “jots” and a QIS may have a gigajot or more, read out at 1000 fps, for a data rate exceeding 1 Tb/s. Basically, we are trying to count photons as they arrive at the sensor. This paper reviews the QIS concept and its imaging characteristics. Recent progress towards realizing the QIS for commercial and scientific purposes is discussed. This includes implementation of a pump-gate jot device in a 65 nm CIS BSI process yielding read noise as low as 0.22 e− r.m.s. and conversion gain as high as 420 µV/e−, power efficient readout electronics, currently as low as 0.4 pJ/b in the same process, creating high dynamic range images from jot data, and understanding the imaging characteristics of single-bit and multi-bit QIS devices. The QIS represents a possible major paradigm shift in image capture.

85 citations

Journal ArticleDOI
TL;DR: This paper presents a robust, low-power and compact ion-sensitive field-effect transistor (ISFET) sensing front-end for pH reaction monitoring using unmodified CMOS.
Abstract: This paper presents a robust, low-power and compact ion-sensitive field-effect transistor (ISFET) sensing front-end for pH reaction monitoring using unmodified CMOS. Robustness is achieved by overcoming problems of DC offset due to trapped charge and transcoductance reduction due to capacitive division, which commonly exist with implementation of ISFETs in CMOS. Through direct feedback to the floating gate and a low-leakage switching scheme, all the unwanted factors are eliminated while the output is capable of tracking a pH reaction which occurs at the sensing surface. This is confirmed through measured results of multiple devices of different sensing areas, achieving a mean amplification of 1.28 over all fabricated devices and pH sensitivity of 42.1 mV/pH. The front-end is also capable of compensating for accumulated drift using the designed switching scheme by resetting the floating gate voltage. The circuit has been implemented in a commercially-available 0.35 $\mu$ m CMOS technology achieving a combined chemical and electrical output RMS noise of 3.1 mV at a power consumption of 848.1 nW which is capable of detecting pH changes as small as 0.06 pH.

79 citations

Journal ArticleDOI
TL;DR: In this article, an analytical noise calculation is presented to derive the impact of process and design parameters on $1/f$ and thermal noise for a low-noise CMOS image sensor (CIS) readout chain.
Abstract: In this paper, an analytical noise calculation is presented to derive the impact of process and design parameters on $1/f$ and thermal noise for a low-noise CMOS image sensor (CIS) readout chain. It is shown that dramatic noise reduction is obtained by using a thin-oxide transistor as the source follower of a typical 4T pixel. This approach is confirmed by a test chip designed in a 180-nm CIS process and embedding small arrays of the proposed new pixels together with state-of-the-art 4T pixels for comparison. The new pixels feature a pitch of 7.5 $\mu \text{m}$ and a fill factor of 66%. A 0.4e- rms input-referred noise and a 185- $\mu \text{V}$ /e- conversion gain are obtained. Compared with state-of-the-art pixels, also present onto the test chip, the rms noise is divided by more than 2 and the conversion gain is multiplied by 2.2.

55 citations

Journal ArticleDOI
TL;DR: A high-sensitivity ion-sensitive field-effect transistor sensor that is small sized, cost-efficient, and massively fabricated in a standard 65-nm complementary metal–oxide–semiconductor process has great potential for food safety detection.
Abstract: Foodborne bacteria, inducing outbreaks of infection or poisoning, have posed great threats to food safety. Potentiometric sensors can identify bacteria levels in food by measuring medium's pH changes. However, most of these sensors face the limitation of low sensitivity and high cost. In this paper, we developed a high-sensitivity ion-sensitive field-effect transistor sensor. It is small sized, cost-efficient, and can be massively fabricated in a standard 65-nm complementary metal–oxide–semiconductor process. A subthreshold pH-to-time-to-voltage conversion scheme was proposed to improve the sensitivity. Furthermore, design parameters, such as chemical sensing area, transistor size, and discharging time, were optimized to enhance the performance. The intrinsic sensitivity of passivation membrane was calculated as 33.2 mV/pH. It was amplified to 123.8 mV/pH with a 0.01-pH resolution, which greatly exceeded 6.3 mV/pH observed in a traditional source-follower based readout structure. The sensing system was applied to Escherichia coli ( E. coli ) detection with densities ranging from 14 to 140 cfu/mL. Compared to the conventional direct plate counting method (24 h), more efficient sixfold smaller screening time (4 h) was achieved to differentiate samples’ E. coli levels. The demonstrated portable, time-saving, and low-cost prescreen system has great potential for food safety detection.

54 citations