Yanzhang Lin

Bio: Yanzhang Lin is an academic researcher from Southeast University. The author has contributed to research in topics: Silicon & Substrate (electronics). The author has an hindex of 3, co-authored 6 publications receiving 33 citations.

A Review of Superjunction Vertical Diffused MOSFET

Abstract: Superjunction has arguably been the most creative and important concept in power device field Superjunction vertical diffused MOSFET (SJ VDMOS) has been commercialized and the research effort to l

High voltage isolation structure based on silicon on insulator

Abstract: A high voltage isolation structure based on silicon on an insulator includes that a surface passivation layer is arranged on an N-type epitaxial layer in a silicon structure on the insulator, a high voltage circuit area, a multi-deep-groove isolation structure and a low voltage circuit area are arranged in the N-type epitaxial layer, the high voltage circuit area is enclosed by the multi-deep-groove isolation structure, and the multi-deep-groove isolation structure is composed of 2 to 20 deep groove isolation structures. The high voltage isolation structure is characterized in that a high-resistance polycrystalline silicon field plate is arranged on the surface passivation layer, the N-type epitaxial layer of the high voltage circuit area and the low voltage circuit area is electrically connected with electrode contact holes, and the N-type epitaxial layer between every adjacent deep groove isolation structures is electrically connected with middle electrode contact holes. Two ends of the high-resistance polycrystalline silicon field plate are respectively electrically connected with the electrode contact holes in the high voltage circuit area and the low voltage circuit area, and the high-resistance polycrystalline silicon field plate is sequentially electrically connected with each electrode contact hole from inside to outside.

A novel compact isolated structure for 600V Gate Drive IC

Abstract: A novel compact isolation structure for high voltage Gate Drive IC is proposed in this paper. As compared with the conventional isolation structure, the proposed structure can achieve the same breakdown capacity with smaller area by adding N-well islands into P-well region which located between LDMOS (Lateral double diffused MOS) and HVJT (high voltage junction termination) region. Moreover, there is no punch through risk in the region between LDMOS and High-side in proposed structure. Finally, a 600V isolation structure is realized with its drift length is only 49µm.

Terminal structure of superjunction VDMOS with discontinuous surface field oxidation layer

Abstract: A terminal structure of a superjunction VDMOS with a discontinuous surface field oxidation layer is disclosed. The structure comprises an annular N-type heavy doping silicon substrate which is used as a drain region. An inner border and an outer border of the N-type heavy doping silicon substrate are in a rectangle shape. A drain electrode metal is arranged on a lower surface of the N-type heavy doping silicon substrate. An N-type doping silicon extension layer is arranged on an upper surface of the N-type heavy doping silicon substrate. A superjunction structure is arranged on the N-type doping silicon extension layer. The superjunction structure comprises: P-type doping-silicon columnar areas and N-type doping-silicon columnar areas. And the P-type doping-silicon columnar areas and the N-type doping-silicon columnar areas are vertically alternatively arranged along the terminal structure. The terminal structure is characterized in that: a silica area and bar-shaped silica are arranged on the superjunction structure; the bar-shaped silica is positioned on a longitudinal side of the terminal structure and is vertically parallelly arranged along the terminal structure; the silica area covers a lateral side of the terminal structure.

Terminal structure of super junction VDMOS

Abstract: The utility model provides a terminal structure of a super junction VDMOS. The terminal structure of the super junction VDMOS includes an N-type heavy doping silicon substrate that also functions as a drain region. A drain electrode metal is arranged on the lower surface of the N-type heavy doping silicon substrate. An N-type doping silicon epitaxial layer is arranged on the upper surface of the N-type heavy doping silicon substrate. A super junction structure is arranged on the N-type doping silicon epitaxial layer. The super junction structure includes a P-type doping silicon columnar area and an N-type doping silicon columnar area. The P-type doping silicon columnar area and the N-type doping silicon columnar area are arranged alternately in a staggered pattern. A silica layer is arranged on the super junction structure. It is characterized in that a row of N-type doping silicon areas is arranged on the top of the P-type doping silicon columnar area while a row of P-type doping silicon areas is arranged on the top of the N-type doping silicon columnar area.

Design and Optimization of SiC Super-Junction MOSFET Using Vertical Variation Doping Profile

Abstract: In this paper, uniformly doped drift region of silicon carbide (SiC) super-junction (SJ) MOSFET is replaced with vertical variable doping profile (VVD) to achieve a better tradeoff between breakdown voltage (BV) and specific ON-resistance ( ${R}_{\text {sp,on}}$ ). While it is known that the SJ device consists of two vertical columns of n- and p-type, SJ VVD feature lies in increasing the doping concentration from top to bottom in the N-column and vice-versa in the P-column within the drift region. The proposed SJ VVD allows $\text {R}_{{\text {sp, on}}}$ to reduce further due to increased average doping concentration in conducting N-column and BV to increase further due to shifting of an electric field from corners to the center of the drift region. BV and ${R}_{\text {sp,on}}$ improved by 10% in an SJ VVD MOSFET and these parameters follow linear relationship similar to SJ MOSFET. The 2-D numerical simulations from Synopsys TCAD are used for investigating the static and dynamic characteristics of the device. In addition to 30% improvement in Baliga figure of merit, 35% improvement is obtained over SJ MOSFET in turn on and turn off switching energies for a clamped inductive circuit at 1200 V–20 A. Improved dynamic characteristics of SJ VVD can be attributed to reduction in gate charge ( ${Q}_{g}$ ) and miller capacitance ( ${c}_{\text {rss}}$ ) compared to SJ MOSFET.

Review of Silicon Carbide Processing for Power MOSFET

Abstract: Owing to the superior properties of silicon carbide (SiC), such as higher breakdown voltage, higher thermal conductivity, higher operating frequency, higher operating temperature, and higher saturation drift velocity, SiC has attracted much attention from researchers and the industry for decades. With the advances in material science and processing technology, many power applications such as new smart energy vehicles, power converters, inverters, and power supplies are being realized using SiC power devices. In particular, SiC MOSFETs are generally chosen to be used as a power device due to their ability to achieve lower on-resistance, reduced switching losses, and high switching speeds than the silicon counterpart and have been commercialized extensively in recent years. A general review of the critical processing steps for manufacturing SiC MOSFETs, types of SiC MOSFETs, and power applications based on SiC power devices are covered in this paper. Additionally, the reliability issues of SiC power MOSFET are also briefly summarized.

Power semiconductor devices, structures, and related methods

Abstract: Power semiconductor devices, and related methods, where majority carrier flow is divided into paralleled flows through two drift regions of opposite conductivity types.

Novel Superjunction LDMOS With a High- K Dielectric Trench by TCAD Simulation Study

Abstract: A novel superjunction (SJ) lateral double-diffused MOSFET (LDMOS) with a deep High- K (HK) dielectric trench (HK SJ-LDMOS) is proposed and its mechanism is investigated by Technology Computer Aided Design (TCAD) simulations. The HK dielectric trench is embedded under the n+ drain, which is connected with the drain electrode. In the OFF-state, the reshaping effect of HK trench enhances the bulk electric field strength and weakens the peak electric field around the edge of the drain diffusion, which increases the breakdown voltage (BV). Moreover, because of the assistant depletion effect by the HK trench, a lower resistivity substrate is allowed for HK SJ-LDMOS, which also increases the doping concentration of the n-type buffer layer under the SJ layer of HK SJ-LDMOS, correspondingly. Thus, a lower specific ON-resistance ( ${R}_{ \mathrm{ ON},\text {sp}}$ ) is also obtained. Simulation results show that the BV increases by 35.2% in comparison with the conventional buffered SJ-LDMOS with the same drift length. Moreover, HK SJ-LDMOS presents an excellent figure of merit, which is two times higher than that of the conventional buffered SJ-LDMOS.

Review and Characterization of Gallium Nitride Power Devices

Abstract: Gallium Nitride (GaN) power devices are an emerging technology that have only recently become available commercially. This new technology enables the design of converters at higher frequencies and efficiencies than those achievable with conventional Si devices. This thesis reviews the characteristics and commercial status of both vertical and lateral GaN power devices from the user perspective, providing the background necessary to understand the significance of these recent developments. Additionally, the challenges encountered in GaN-based converter design are considered, such as the consequences of faster switching on gate driver design and board layout. Other issues include the unique reverse conduction behavior, dynamic on-resistance, breakdown mechanisms, thermal design, device availability, and reliability qualification. Static and dynamic characterization was then performed across the full current, voltage, and temperature range of this device to enable effective GaN-based converter design. Static testing was performed with a curve tracer and precision impedance analyzer. A double pulse test setup was constructed and used to measure switching loss and time at the fastest achievable switching speed, and the subsequent overvoltages due to the fast switching were characterized. The results were also analyzed to characterize the effects of cross-talk in the active and synchronous devices of a phaseleg topology with enhancement-mode GaN HFETs. Based on these results and analysis, an accurate loss model was developed for the device under test. Based on analysis of these characterization results, a simplified model was developed to describe the overall switching behavior and some unique features of the device. The consequences of the Miller effect during the turn-on transient were studied to show that no Miller plateau occurs, but rather a decreased gate voltage slope, followed by a sharp drop. The significance of this distinction is derived and explained. GaN performance at elevated temperature was also studied, because turn-on time increases significantly with temperature, and turn-on losses increase as a