Yao-Ting Wang

Bio: Yao-Ting Wang is an academic researcher from Synopsys. The author has contributed to research in topics: Photolithography & Phase-shift mask. The author has an hindex of 4, co-authored 5 publications receiving 571 citations.

Phase shifting circuit manufacture method and apparatus

Abstract: A method and apparatus for creating a phase shifting mask and a structure mask for shrinking integrated circuit designs. One embodiment of the invention includes using a two mask process. The first mask is a phase shift mask and the second mask is a single phase structure mask. The phase shift mask primarily defines regions requiring phase shifting. The single phase structure mask primarily defines regions not requiring phase shifting. The single phase structure mask also prevents the erasure of the phase shifting regions and prevents the creation of undesirable artifact regions that would otherwise be created by the phase shift mask. Both masks are derived from a set of masks used in a larger minimum dimension process technology.

Method and apparatus for data hierarchy maintenance in a system for mask description

Abstract: A method and apparatus for performing an operation on hierarchically described integrated circuit layouts such that the original hierarchy of the layout is maintained is provided. The method comprises providing a hierarchically described layout as a first input and providing a particular set of operating criteria corresponding to the operation to be performed as a second input. The mask operation, which may include operations such as OPC and logical operations such as NOT and OR, is then performed on the layout in accordance with the particular set of operating criteria. A first program data comprising hierarchically configured correction data corresponding to the hierarchically described layout is then generated in response to the layout operation such that if the first program data were applied to the flattened layout an output comprising data representative of the result of performing the operation on the layout would be generated. As the first program data is maintained in a true hierarchical format, layouts which are operated upon in accordance with this method are able to be processed through conventional design rule checkers. Further, this method is capable of being applied to all types of layouts including light and dark field designs and phase shifting layouts.

Visual analysis and verification system using advanced tools

Abstract: A system and method of analyzing defects on a mask used in lithography are provided. A defect area image is provided as a first input, a set of lithography parameters is provided as a second input, and a set of metrology data is provided as a third input. The defect area image comprises an image of a portion of the mask. A simulated image can be generated in response to the first input. The simulated image comprises a simulation of an image that would be printed on a wafer if the wafer were exposed to a radiation source directed at the portion of the mask. The characteristics of the radiation source comprise the set of lithography parameters and the characteristics of the mask comprise the set of metrology data.

Practicing extension of 248-nm DUV optical lithography using trim-mask PSM

Abstract: It is becoming increasingly clear that semiconductor manufacturers must rise to the challenge of extending optical microlithography beyond what is forecast by the current SIA roadmap. Capabilities must be developed that allow the use of conventional exposure methods beyond their designed capabilities. This is driven in part by the desire to keep up with the predictions of Moore's law. Additional motivation for implementing optical extension methods is provided by the need for workable alternatives in the event that manufacturing capable post-optical lithography is delayed beyond 2003. Major programs are in place at semiconductor manufacturers, development organization, and EDA software providers to continue optical microlithography far past what were once thought to be recognized limits. This paper details efforts undertaken by Motorola to produce functional high density silicon devices with sub-eighth micron transistor gates using DUV microlithography. The preferred enhancement technique discussed here utilizes complementary or dual-exposure trim-mask PSM which incorporates a combined exposure of both Levenson hard shifter and binary trim masks.

Method and system for lithographic mask inspection

Abstract: A method and apparatus for inspecting a photolithography mask (420) for defects is provided The inspection method comprises providing a defect area image (430) to an image simulator (460) wherein the defect area image is an image of a portion of a photolithography mask, and providing a set of lithography parameters (445) as a second input to the image simulator The defect area image (442) may be provided by an inspection tool which scans (430) the photolithography mask for defects using a high resolution microscope and captures images of areas of the mask around identified potential defects The image simulator generates a first simulated image in response to the defect area image (442) and the set of lithography parameters The first simulated image (470) is a simulation of an image which would be printed on a wafer if the wafer were to be exposed to an illumination source directed through the portion of the mask The method may also include providing a second simulated image which is a simulation of the wafer print of the portion of the design mask which corresponds to the portion represented by the defect area image The method also provides for the comparison of the first and second simulated images in order to determine the printability of any identified potential defects on the photolithography mask A method of determining the process window effect of any identified potential defects is also provided for

Methods and systems for utilizing design data in combination with inspection data

Abstract: Various methods and systems for utilizing design data in combination with inspection data are provided. One computer-implemented method for binning defects detected on a wafer includes comparing portions of design data proximate positions of the defects in design data space. The method also includes determining if the design data in the portions is at least similar based on results of the comparing step. In addition, the method includes binning the defects in groups such that the portions of the design data proximate the positions of the defects in each of the groups are at least similar. The method further includes storing results of the binning step in a storage medium.

Integrated verification and manufacturability tool

Abstract: An integrated verification and manufacturability tool provides more efficient verification of integrated device designs than verification using several different verification tools. The integrated verification and manufacturability includes a hierarchical database to store shared design data accessed by multiple verification tool components (e.g., layout versus schematic, design rule check, optical process correction, phase shift mask assignment and machine language conversion). The hierarchical database includes representations of one or more additional, or intermediate layer structures that are created and used by the verification tool components for operations performed on the design being verified. Use of a single hierarchical database having shared data for access and use by multiple verification components streamlines the verification process, which provides an improved verification tool.

Step and repeat imprint lithography systems

Abstract: Described are systems for patterning a substrate by imprint lithography. Imprint lithography systems include an imprint head configured to hold a template in a spaced relation to a substrate. The imprint lithography system is configured to dispense an activating light curable liquid onto a substrate or template. The system includes a light source that applies activating light to cure the activating light curable liquid.

System and method for lithography simulation

Abstract: In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques.

Generating an instance-based representation of a design hierarchy

Abstract: One embodiment of the invention provides a system for generating an instance-based representation of a set of geometrical features that comprise a layout of a circuit on a semiconductor chip. This system operates by receiving a design hierarchy specifying the layout of the circuit, wherein the design hierarchy includes a set of hierarchically organized nodes. Within this design hierarchy, a given node specifies a geometrical feature, which can be comprised of lower-level geometrical features. These lower-level geometrical features are represented by lower-level nodes that appear under the given node in the design hierarchy. Furthermore, the layout of the given node is specified by a first cell, which in turn specifies the layout of one or more nodes in the design hierarchy. For each node within the design hierarchy, the system determines how interactions with the node's siblings and/or parent, and possibly other surrounding geometries, change the layout of the node as specified by the first cell. If the changes result in a new node for which no instance has been created, the system creates a new instance for the node.