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Yao-Wen Chang
Researcher at National Taiwan University
Publications - 403
Citations - 9131
Yao-Wen Chang is an academic researcher from National Taiwan University. The author has contributed to research in topics: Routing (electronic design automation) & Equal-cost multi-path routing. The author has an hindex of 45, co-authored 382 publications receiving 8378 citations. Previous affiliations of Yao-Wen Chang include MediaTek & National Chiao Tung University.
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Journal ArticleDOI
Full-Chip Routing Considering Double-Via Insertion
TL;DR: A new full-chip gridless routing system considering double-via insertion for yield enhancement and a new redundant-via aware detailed maze routing algorithm (which could be applied to both gridless and grid-based routing).
Journal ArticleDOI
A Network-Flow-Based RDL Routing Algorithmz for Flip-Chip Design
TL;DR: This paper proposes the first router for the flip-chip package in the literature that adopts a two-stage technique of global routing followed by detailed routing, and uses the network flow algorithm to solve the assignment problem from the wire-bonding pads to the bump pads and then create the global path for each net.
Proceedings ArticleDOI
NTUplace: a ratio partitioning based placement algorithm for large-scale mixed-size designs
TL;DR: This paper presents a hierarchical ratio partitioning based placement algorithm that works in a hierarchical manner and integrates net-weighting partitioning, whitespace management, look-ahead bipartitioning, and fast legalization to handle the large-scale mixed-size placement problems.
Journal ArticleDOI
TSV-Aware Analytical Placement for 3-D IC Designs Based on a Novel Weighted-Average Wirelength Model
TL;DR: This paper proposes a new 3-D cell placement algorithm that can additionally consider the sizes of TSVs and the physical positions for TSV insertion during placement, and can achieve the best routed wirelength, TSV counts, and total silicon area, in shortest running time.
Proceedings ArticleDOI
Temporal floorplanning using the T-tree formulation
TL;DR: This work presents a tree-based data structure, called T-trees, to represent the spatial and temporal relations among tasks and develops an efficient packing method and derive the condition to ensure the satisfaction of precedence constraints which model the temporal ordering among tasks induced by the execution of dynamically reconfigurable FPGAs.