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Yasuhiro Sugimoto

Other affiliations: Toshiba
Bio: Yasuhiro Sugimoto is an academic researcher from Chuo University. The author has contributed to research in topics: CMOS & Sample and hold. The author has an hindex of 11, co-authored 110 publications receiving 588 citations. Previous affiliations of Yasuhiro Sugimoto include Toshiba.


Papers
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Patent
24 Sep 1986
TL;DR: In this article, a level conversion circuit consisting of an input terminal for applying a voltage signal of predetermined amplitude level, an output terminal for supplying a signal, the amplitude level of which is different from that of the voltage level corresponding to the signal applied to the input terminal, which is connected to the drain of the third MOS transistor.
Abstract: This invention provides a level conversion circuit comprising: an input terminal means for applying a voltage signal of predetermined amplitude level; an inverter circuit means applied by a first power supply and a second power supply and connected to the input terminal; a first MOS transistor of a first channel type, the source of which is connected to the second power supply, and the gate of which is connected to the output of the inverter circuit means; a current-voltage conversion means for converting from a source-drain current change of the first MOS transistor to voltage change, a first terminal of which is connected to the drain of the first MOS transistor, and a second terminal of which is connected to a third power supply; a second MOS transistor of the second channel type, the source of which is connected to the third power supply, and the gate of which is connected to the first terminal of the current-voltage conversion means; a third MOS transistor of the first channel type, the gate of which is connected to the input terminal, and source of which is connected to the second power supply, and drain of which is connected to the drain of the second MOS transistor; and an output terminal means for supplying a signal, the amplitude level of which is different from that of the voltage level corresponding to the signal applied to the input terminal, which is connected to the drain of the third MOS transistor.

62 citations

Journal ArticleDOI
TL;DR: In this article, a new video-speed current-mode CMOS sample-and-hold IC has been developed, which operates with a supply voltage as low as 1.5 V, a signal-to-noise ratio (S/N) of 57 dB and 54 dB with a 1-MHz input signal at clock frequencies of 20 and 30 MHz, and a power dissipation of 2.3 mW.
Abstract: A new video-speed current-mode CMOS sample-and-hold IC has been developed. It operates with a supply voltage as low as 1.5 V, a signal-to-noise ratio (S/N) of 57 dB and 54 dB with a 1-MHz input signal at clock frequencies of 20 and 30 MHz, and a power dissipation of 2.3 mW. It consists of current-mirror circuits with the node voltages at the input and the output terminals which are kept constant in all phases of the input signal by the use of low-voltage operational amplifiers; this reduces the signal current dependency. The low-voltage operational amplifier consists of a MOS transistor and a constant current source in a common-gate amplifier configuration. Only two analog switches in differential form were used to construct the differential sample-and-hold circuit. This minimizes the error caused by the switch feed through, and thus high accuracy can be realized. Since there is no analog switch in the input path, it is possible to convert the input signal voltage to a current by simply connecting an external resistor. The circuit was fabricated using standard 0.6-/spl mu/m MOS devices with normal threshold voltages (V/sub th/) of +0.7 V (nMOS) and -0.7 V (pMOS).

30 citations

Patent
06 Nov 2001
TL;DR: In this paper, a sample-and-hold circuit using a completely differential type operational amplifier circuit, to promote operational stability, to restrain a variation in a balance point of a middle value of differential output signals and to promote stability and accuracy of an A/D converter are achieved.
Abstract: In a sample-and-hold circuit using a completely differential type operational amplifier circuit, to promote operational stability, to restrain a variation in a balance point of a middle value of differential output signals and to promote stability and accuracy of an A/D converter are achieved by a constitution as bellow. There is provided a common phase feedback circuit 2, common phase feedback hold capacitors CF1 and CF2 of which are connected to input terminals IN1 and IN2 of a completely differential type operational amplifier circuit 1, during a sample period, by way of reset switches RS1 and RS2 connecting the input terminals IN1 and IN2 and output terminals OUT1 and OUT2 of the completely differential type operational amplifier circuit 1, the common phase feedback hold capacitors CF1 and CF2 are charged to thereby determine a balance point of a middle value of differential output signals from the output terminals OUT1 and OUT2 and during a hold period, the balance point of the middle value of the differential output signals is maintained by electric charge charged to the common phase feedback hold capacitors CF1 and CF2 regardless of the differential output signals.

30 citations

Patent
23 Mar 1987
TL;DR: In this paper, the merits of the MOS transistors and the bipolar transistors can be demonstrated by the particular combination of the two different kinds of transistors in the logical circuit, thereby increasing the current driving performance while reducing power consumption without making the size of the logical NAND circuit large.
Abstract: Logical NAND circuits, each consisting of a logical operational portion, an output control portion comprising the combination of a bipolar transistor and a plurality of NMOS transistors, and an output portion comprising first and second bipolar transistors connected in series between power supply voltage and the ground in which the merits of the MOS transistors and the bipolar transistors can be demonstrated by the particular combination of the two different kinds of the transistors in the logical circuit, thereby increasing the current driving performance while reducing power consumption without making the size of the logical circuit large.

22 citations

Proceedings ArticleDOI
09 Jun 1997
TL;DR: In this paper, a CMOS ring-oscillator type VCO circuit with inphase (I) and quadrature-phase (Q) outputs has been designed by using 0.6 /spl mu/m MOS devices.
Abstract: A CMOS ring-oscillator type VCO circuit with inphase (I) and quadrature-phase (Q) outputs has been designed by using 0.6 /spl mu/m MOS devices. This VCO has demonstrated 1 V and 1 GHz operational capabilities. Two differential delay cells has been used as one delay section and the transitions of the delay cell outputs have been combined, and thus the 1 GHz 1/Q output generation has been realized. The current-mode approach throughout the design has resulted in the extremely low voltage operation. The simulation results show more than 1.4 GHz oscillation frequency from a 1 V power supply, and less than /spl plusmn/1 phase error for I/Q outputs when Vth variation is 10 mV.

20 citations


Cited by
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Book
01 Jan 1977
TL;DR: In this article, the authors combine bipolar, CMOS and BiCMOS analog integrated circuits into a unified treatment that stresses their commonalities and highlights their differences, and provide valuable insights into the relative strengths and weaknesses of these important technologies.
Abstract: The Fifth Edition of this academically rigorous text provides a comprehensive treatment of analog integrated circuit analysis and design starting from the basics and through current industrial practices. The authors combine bipolar, CMOS and BiCMOS analog integrated-circuit design into a unified treatment that stresses their commonalities and highlights their differences. The comprehensive coverage of the material will provide the student with valuable insights into the relative strengths and weaknesses of these important technologies.

4,717 citations

Journal ArticleDOI
TL;DR: A digital-domain self-calibration technique, which can directly measure and cancel code errors in multistep conversions, is developed to improve the linearity of multi-step analog-to-digital converters (ADCs).
Abstract: A digital-domain self-calibration technique, which can directly measure and cancel code errors in multistep conversions, is developed to improve the linearity of multi-step analog-to-digital converters (ADCs). While conventional self-calibration techniques require separate digital-to-analog converters (DACs) for calibration purpose to subtract nonlinearity errors in the analog domain, the proposed digital calibration technique uses add-on digital logic to subtract nonlinearity errors digitally from uncalibrated digital outputs. In a prototype 12-b fully differential two-step ADC implemented using a 2- mu m n-well CMOS technology, this technique cancels MOS switch feedthrough, op-amp offsets, and interstage gain errors simultaneously, and improves total harmonic distortion from -64 to -77 dB. >

219 citations

Journal ArticleDOI
TL;DR: In this paper, the design of three and nine-stage voltage-controlled ring oscillators that were fabricated in TSMC 0.18/spl mu/m CMOS technology with oscillation frequencies up to 5.9 GHz was presented.
Abstract: This paper presents the design of three- and nine-stage voltage-controlled ring oscillators that were fabricated in TSMC 0.18-/spl mu/m CMOS technology with oscillation frequencies up to 5.9 GHz. The circuits use a multiple-pass loop architecture and delay stages with cross-coupled FETs to aid in the switching speed and to improve the noise parameters. Measurements show that the oscillators have linear frequency-voltage characteristics over a wide tuning range, with the three- and nine-stage rings resulting in frequency ranges of 5.16-5.93 GHz and 1.1-1.86 GHz, respectively. The measured phase noise of the nine-stage ring oscillator was -105.5 dBc/Hz at a 1-MHz offset from a 1.81-GHz center frequency, whereas the value for the three-stage ring oscillator was simulated to be -99.5 dBc/Hz at a 1-MHz offset from a 5.79-GHz center frequency.

209 citations

Journal ArticleDOI
14 Oct 2010
TL;DR: A 16-bit 250 MS/s ADC fabricated on a 0.18 BiCMOS process with an integrated input buffer with a new linearization technique that improves its distortion by 5-10 dB and lowers its power consumption by 70% relative to the state of the art.
Abstract: This paper describes a 16-bit 250 MS/s ADC fabricated on a 0.18 BiCMOS process. The ADC has an integrated input buffer with a new linearization technique that improves its distortion by 5-10 dB and lowers its power consumption by 70% relative to the state of the art. It demonstrates a new background calibration technique to correct the residue amplifier (RA) gain errors and lower its power consumption. This summing node sampling (SNS) calibration technique is based on sampling the summing-node voltage of the residue amplifier and using it with the corresponding residue to estimate the amplifier open loop gain. The ADC achieves an SNDR of 76.5 dB and consumes 850 mW from a 1.8 V supply, while the input buffer consumes 150 mW from a 3 V supply. Up to 125 MS/s, the SFDR is greater than 100 dB for input frequencies up to 100 MHz and 90 dB up to 300 MHz input frequency. At 250 MS/s, the SFDR is greater than 95 dB up to 100MHz and 85 dB up to 300 MHz.

171 citations