Ye Qiang

Bio: Ye Qiang is an academic researcher from Xidian University. The author has contributed to research in topics: Low-dropout regulator & Linear regulator. The author has an hindex of 1, co-authored 1 publications receiving 3 citations.

A Fast-Transient Response and Low-Quiescent Current CMOS Low-Dropout Regulator

Abstract: A low-dropout regulator(LDO) with fast-transient response speed is presented by utilizing the proposed transient response enhancement(TRE) circuit,which doesn't bring the quiescent current increase.The proposed LDO has been fabricated in a 0.5μm standard CMOS process,and the die area is 0.49mm2.The proposed LDO dissipates 23μA quiescent current at no-load condition and is able to deliver up to 200mA load current.With a 1μF output capacitor,the maximum transient output-voltage variation is within 3.5% of the output voltage with load step changes of 200mA/100ns.

A 3 A sink/source current fast transient response low-dropout G m driven linear regulator

Abstract: A 3 A sink/source Gm-driven CMOS low-dropout regulator (LDO), specially designed for low input voltage and low cost, is presented by utilizing the structure of a current mirror Gm (transconductance) driving technique, which provides high stability as well as a fast load transient response. The proposed LDO was fabricated by a 0.5 ?m standard CMOS process, and the die size is as small as 1.0 mm2. The proposed LDO dissipates 220 ?A of quiescent current in no-load conditions and is able to deliver up to 3 A of load current. The measured results show that the output voltage can be resumed within 2 ?s with a less than 1 mV overshoot and undershoot in the output current step from ?1.8 to 1.8 A with a 0.1 ?s rising and falling time at three 10 ?F ceramic capacitors.

A micro-power LDO with piecewise voltage foldback current limit protection

Abstract: To achieve a constant current limit, low power consumption and high driving capability, a micro-power LDO with a piecewise voltage-foldback current-limit circuit is presented. The current-limit threshold is dynamically adjusted to achieve a maximum driving capability and lower quiescent current of only 300 nA. To increase the loop stability of the proposed LDO, a high impedance transconductance buffer under a micro quiescent current is designed for splitting the pole that exists at the gate of the pass transistor to the dominant pole, and a zero is designed for the purpose of the second pole phase compensation. The proposed LDO is fabricated in a BiCMOS process. The measurement results show that the short-circuit current of the LDO is 190 mA, the constant limit current under a high drop-out voltage is 440 mA, and the maximum load current under a low drop-out voltage is up to 800 mA. In addition, the quiescent current of the LDO is only 7 μA, the load regulation is about 0.56% on full scale, the line regulation is about 0.012%/V, the PSRR at 120 Hz is 58 dB and the drop-out voltage is only 70 mV when the load current is 250 mA.

Design and implementation of a 3-A source and sink linear regulator for bus terminators

Abstract: According to the requirements of the bus terminal regulator, a linear regulator with 3-A source-sink current ability is presented. The use of the NMOS pass transistor and load current feedback technique enhances the system current ability and response speed. The method of adaptive zero compensation realizes loop stability over the whole load range for either source or sink loop. Furthermore, the transconductance matching technique reduces the shoot-through current through the output stage to less than 3 μA. The regulator has been fabricated with a 0.6-μm 30 V BCD process successfully, and the area size is about 1 mm2. With a 20 μF output capacitor, the maximum transient output-voltage variation is within 3.5% of the output voltage with load step changes of ±2 A/1 μs. At the load range of ±3 A, the variation of output voltage is less than ±15 mV.