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Author

Yeon-hee Kim

Bio: Yeon-hee Kim is an academic researcher from Samsung. The author has contributed to research in topics: Layer (electronics) & Etching (microfabrication). The author has an hindex of 6, co-authored 19 publications receiving 1325 citations.

Papers
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Patent
21 Nov 2007
TL;DR: In this paper, a Ga-In-Zn-O-O (GINZN-O) thin film etching method was proposed, where the mask layer was used as an etch barrier.
Abstract: Example methods may provide a thin film etching method. Example thin film etching methods may include forming a Ga—In—Zn—O film on a substrate, forming a mask layer covering a portion of the Ga—In—Zn—O film, and etching the Ga—In—Zn—O film using the mask layer as an etch barrier, wherein an etching gas used in the etching includes chlorine. The etching gas may further include an alkane (CnH2n+2) and H2 gas. The chlorine gas may be, for example, Cl2, BCl3, and/or CCl3, and the alkane gas may be, for example, CH4.

1,010 citations

Proceedings ArticleDOI
01 Dec 2007
TL;DR: In this article, a 2-stack 8-times-8 array with 0.5 mumtimes0.5 cells was proposed to demonstrate the feasibility of high density stacked RRAM.
Abstract: We have successfully integrated a 2-stack 8times8 array 1D- lR (one diode-one resistor) structure with 0.5 mumtimes0.5 mum cells in order to demonstrate the feasibility of high density stacked RRAM. p-CuOx/n-InZnOx heterojunction thin film was used for the first time as a oxide diode which shows increased current density of two orders over our previous p-NiOx/n-TiOx oxide diode. And Ti-doped NiO was used for the storage node. No limitation to the number of stacks has been observed from our results. Cell and device properties of our cross-point structure 8times8 array are reported. In addition, all fabrication processes were done at room temperature without other dedicated facilities or processes allowing for compatibility with current CMOS technology. Bi-stable switching for 1D-1R memory was demonstrated for our 2-stack cross-point structures showing excellent behavior for both diode and storage nodes. The forward current density for p-CuOx/n-IZOx diodes was over 104A/cm2, and the operation voltage for the storage node with diode attached was around 3 V.

266 citations

Journal ArticleDOI
TL;DR: In this article, a novel approach for the thin film encapsulation (TFE) of organic photo-diode (OPD) for the next generation of organic/inorganic hybrid complementary metal oxide semiconductor (CMOS) image sensor is reported.

13 citations

Journal ArticleDOI
TL;DR: Wang et al. as discussed by the authors developed wet-process-compatible organic photodetectors by replacing the conventional shadow mask process with photolithography, which suppresses particle deposition during the serial fabrication processes, providing high operational stability.

8 citations

Patent
17 Dec 2015
TL;DR: A transistor is a two-dimensional material including at least one layer that is substantially vertically aligned on the substrate such that an edge of the substrate and the layer extends substantially vertical to the substrate.
Abstract: A transistor includes a substrate, a two-dimensional material including at least one layer that is substantially vertically aligned on the substrate such that an edge of the layer is on the substrate and the layer extends substantially vertical to the substrate, a source electrode and a drain electrode connected to opposite ends of the two-dimensional material, a gate insulation layer on the two-dimensional material between the source electrode and the drain electrode, and a gate electrode on the gate insulation layer. Each layer includes a semiconductor having a two-dimensional crystal structure.

7 citations


Cited by
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Journal ArticleDOI
02 May 2012
TL;DR: The physical mechanism, material properties, and electrical characteristics of a variety of binary metal-oxide resistive switching random access memory (RRAM) are discussed, with a focus on the use of RRAM for nonvolatile memory application.
Abstract: In this paper, recent progress of binary metal-oxide resistive switching random access memory (RRAM) is reviewed. The physical mechanism, material properties, and electrical characteristics of a variety of binary metal-oxide RRAM are discussed, with a focus on the use of RRAM for nonvolatile memory application. A review of recent development of large-scale RRAM arrays is given. Issues such as uniformity, endurance, retention, multibit operation, and scaling trends are discussed.

2,295 citations

Patent
01 Aug 2008
TL;DR: In this article, the oxide semiconductor film has at least a crystallized region in a channel region, which is defined as a region of interest (ROI) for a semiconductor device.
Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

1,501 citations

Journal ArticleDOI
20 Apr 2010
TL;DR: The physics behind this large resistivity contrast between the amorphous and crystalline states in phase change materials is presented and how it is being exploited to create high density PCM is described.
Abstract: In this paper, recent progress of phase change memory (PCM) is reviewed. The electrical and thermal properties of phase change materials are surveyed with a focus on the scalability of the materials and their impact on device design. Innovations in the device structure, memory cell selector, and strategies for achieving multibit operation and 3-D, multilayer high-density memory arrays are described. The scaling properties of PCM are illustrated with recent experimental results using special device test structures and novel material synthesis. Factors affecting the reliability of PCM are discussed.

1,488 citations

Patent
25 Sep 2013
TL;DR: In this paper, a connection terminal portion is provided with a plurality of connection pads which are part of the connection terminal, each of which includes a first connection pad and a second connection pad having a line width different from that of the first one.
Abstract: An object of the present invention is to decrease the resistance of a power supply line, to suppress a voltage drop in the power supply line, and to prevent defective display. A connection terminal portion includes a plurality of connection terminals. The plurality of connection terminals is provided with a plurality of connection pads which is part of the connection terminal. The plurality of connection pads includes a first connection pad and a second connection pad having a line width different from that of the first connection pad. Pitches between the plurality of connection pads are equal to each other.

1,136 citations

Journal ArticleDOI
TL;DR: NVSim is developed, a circuit-level model for NVM performance, energy, and area estimation, which supports various NVM technologies, including STT-RAM, PCRAM, ReRAM, and legacy NAND Flash and is expected to help boost architecture-level NVM-related studies.
Abstract: Various new nonvolatile memory (NVM) technologies have emerged recently. Among all the investigated new NVM candidate technologies, spin-torque-transfer memory (STT-RAM, or MRAM), phase-change random-access memory (PCRAM), and resistive random-access memory (ReRAM) are regarded as the most promising candidates. As the ultimate goal of this NVM research is to deploy them into multiple levels in the memory hierarchy, it is necessary to explore the wide NVM design space and find the proper implementation at different memory hierarchy levels from highly latency-optimized caches to highly density- optimized secondary storage. While abundant tools are available as SRAM/DRAM design assistants, similar tools for NVM designs are currently missing. Thus, in this paper, we develop NVSim, a circuit-level model for NVM performance, energy, and area estimation, which supports various NVM technologies, including STT-RAM, PCRAM, ReRAM, and legacy NAND Flash. NVSim is successfully validated against industrial NVM prototypes, and it is expected to help boost architecture-level NVM-related studies.

1,100 citations