A reconfigurable, protocol indifferent bit stream-processing engine, and related systems and data communication methodologies, are adapted to achieve the goal of providing inter-fabric interoperability among high-speed networks operating a speeds of at least 10 gigabits per second. The bit-stream processing engine operates as an omni-protocol, multi-stage processor that can be configured with appropriate switches and related network elements to create a seamless network fabric that permits interoperability not only among existing communication protocols, but also with the ability to accommodate future communication protocols. The method and systems of the present invention are applicable to networks that include storage networks, communication networks and processor networks.

Omni-protocol engine for reconfigurable bit-stream processing in high-speed networks

Methods, apparatus, and systems for enhancing communication between compute resources and networks in a micro-server environment. Micro-server modules configured to be installed in a server chassis include a plurality of processor subsystems coupled in communication to a shared Network Interface Controller (NIC) via PCIe links. The shared NIC includes at least one Ethernet port and a PCIe block including a shared PCIe interface having a first number of lanes. The PCIe lines between the processor sub-systems and the shared PCIe interface employ a number of lanes that is less than the first number of lanes, and during operation of the micro-server module, the shared NIC is configured to enable each processor sub-system to access the at least one Ethernet port using the PCIe link between that processor sub-system and the shared PCIe block on the shared NIC.

Methods and apparatus for sharing a network interface controller

A control network communication arrangement includes a second protocol embedded into a first protocol in a way that modules supporting the second protocol may be aware of and utilize the first protocol whereas modules supporting only the first protocol may not be aware of the second protocol. Operation of modules using the second protocol does not disturb operation of the modules not configured to use or understand the second protocol. By one approach, the messages sent using the second protocol will be seen as messages sent using the first protocol but not having a message necessary to understand or as needing a particular response. In another approach, modules using the second protocol can be configured to send message during transmission of first protocol messages by other modules, the second protocol messages being triggered off of expected aspects of the message sent under the first protocol.

High Speed Embedded Protocol for Distributed Control Systems

In a particular embodiment, a multi-path bridge circuit includes a backplane input/output (I/O) interface to couple to a local backplane having at least one communication path to a processing node and includes at least one host interface adapted to couple to a corresponding at least one processor. The multi-path bridge circuit further includes logic adapted to identify two or more communication paths through the backplane interface to a destination memory, to divide a data block stored at a source memory into data block portions, and to transfer the data block portions in parallel from the source memory to the destination node via the identified two or more communication paths.

System and method of multi-path data communications

Embodiments of the invention provide systems and methods to implement an object memory fabric. Object memory modules may include object storage storing memory objects, memory object meta-data, and a memory module object directory. Each memory object and/or memory object portion may be created natively within the object memory module and may be a managed at a memory layer. The memory module object directory may index all memory objects and/or portions within the object memory module. A hierarchy of object routers may communicatively couple the object memory modules. Each object router may maintain an object cache state for the memory objects and/or portions contained in object memory modules below the object router in the hierarchy. The hierarchy, based on the object cache state, may behave in aggregate as a single object directory communicatively coupled to all object memory modules and to process requests based on the object cache state.

Utilization of a distributed index to provide object memory fabric coherency

A computing and communication architecture utilizes a serial protocol based switched fabric among circuit cards housed in packaging arrangement. In one embodiment, each circuit card connected to the serial protocol based switched fabric in the packaging arrangement is provided with a protocol processor that enables all of the circuit cards to efficiently provide packet-based serial self-clocked communications at line speed. As a result, it is not necessary to arrange the circuit cards in a hierarchical manner in order to address the problems of switch blocking and related traffic congestion issues that would otherwise limit the implementation of the serial protocol based backplane arrangement for housing circuit cards.

Yi-chang Chou

Papers

Telecommunication and computing platforms with serial packet switched integrated memory access technology

Protocol translation method and bridge device for switched telecommunication and computing platforms

Serial memory and io access architecture and system for switched telecommunication and computing platforms