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Yi-Chiau Huang

Other affiliations: Cornell University
Bio: Yi-Chiau Huang is an academic researcher from Applied Materials. The author has contributed to research in topics: Germanium & Layer (electronics). The author has an hindex of 23, co-authored 98 publications receiving 2406 citations. Previous affiliations of Yi-Chiau Huang include Cornell University.


Papers
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Patent
31 Mar 2008
TL;DR: In this paper, a memory device is provided which includes a floating gate polysilicon layer disposed over source/drain regions of a substrate, a silicon oxynitride layer over an inter-poly dielectric stack disposed over a silicon oxide layer, and a control gate poly silicon layer over the second aluminum oxide layer.
Abstract: Embodiments of the invention provide memory devices and methods for forming memory devices. In one embodiment, a memory device is provided which includes a floating gate polysilicon layer disposed over source/drain regions of a substrate, a silicon oxynitride layer disposed over the floating gate polysilicon layer, a first aluminum oxide layer disposed over the silicon oxynitride layer, a hafnium silicon oxynitride layer disposed over the first aluminum oxide layer, a second aluminum oxide layer disposed over the hafnium silicon oxynitride layer, and a control gate polysilicon layer disposed over the second aluminum oxide layer. In another embodiment, a memory device is provided which includes a control gate polysilicon layer disposed over an inter-poly dielectric stack disposed over a silicon oxide layer disposed over the floating gate polysilicon layer. The inter-poly dielectric stack contains two silicon oxynitride layers separated by a silicon nitride layer.

228 citations

Patent
14 Nov 2006
TL;DR: In this article, a silicon dioxide atomic layer deposition method with pyridine as a catalyst was proposed. But the method was limited to silicon dioxide and water was used as oxidization source while depositing at low temperature.
Abstract: The present invention generally comprises a silicon dioxide atomic layer deposition method. By providing pyridine as a catalyst, water may be utilized as the oxidization source while depositing at a low temperature. Prior to exposing the substrate to the water, the substrate may be exposed to a pyridine soak process. Additionally, the water may be co-flowed to the chamber with the pyridine through separate conduits to reduce interaction prior to entering the chamber. Alternatively, the pyridine may be co-flowed with a silicon precursor that does not react with pyridine.

215 citations

Patent
08 Jan 2013
TL;DR: In this paper, a method for depositing silicon germanium tin (SiGeSn) layer on a substrate is described. But it is not shown how to obtain the SiGeSn layer on the substrate.
Abstract: Methods of depositing silicon germanium tin (SiGeSn) layer on a substrate are disclosed herein. In some embodiments, a method may include co-flowing a silicon source, a germanium source, and a tin source comprising a tin halide to a process chamber at a temperature of about 450 degrees Celsius or below and a pressure of about 100 Torr or below to deposit the SiGeSn layer on a first surface of the substrate. In some embodiments, the tin halide comprises tin tetrachloride (SnCl4).

154 citations

Patent
04 Mar 2013
TL;DR: In this paper, a germanium precursor and a tin precursor are provided to a chamber, and an epitaxial layer is formed on the substrate by either alternating or concurrent flow of a halide gas to etch the surface of the substrate.
Abstract: A method for forming germanium tin layers and the resulting embodiments are described. A germanium precursor and a tin precursor are provided to a chamber, and an epitaxial layer of germanium tin is formed on the substrate. The germanium tin layer is selectively deposited on the semiconductor regions of the substrate and can include thickness regions of varying tin and dopant concentrations. The germanium tin layer can be selectively deposited by either alternating or concurrent flow of a halide gas to etch the surface of the substrate.

152 citations

Patent
26 Apr 2012
TL;DR: In this article, a clean surface of germanium tin or silicon germanIUM tin layers for subsequent deposition is provided, where an overlayer of Ge, doped Ge, another GeSn or SiGeSn layer, an insulator, or a metal can be deposited on a prepared GeSn and SiGesn layer.
Abstract: Methods of preparing a clean surface of germanium tin or silicon germanium tin layers for subsequent deposition are provided. An overlayer of Ge, doped Ge, another GeSn or SiGeSn layer, a doped GeSn or SiGeSn layer, an insulator, or a metal can be deposited on a prepared GeSn or SiGeSn layer by positioning a substrate with an exposed germanium tin or silicon germanium tin layer in a processing chamber, heating the processing chamber and flowing a halide gas into the processing chamber to etch the surface of the substrate using either thermal or plasma assisted etching followed by depositing an overlayer on the substantially oxide free and contaminant free surface. Methods can also include the placement and etching of a sacrificial layer, a thermal clean using rapid thermal annealing, or a process in a plasma of nitrogen trifluoride and ammonia gas.

149 citations


Cited by
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Patent
01 Aug 2008
TL;DR: In this article, the oxide semiconductor film has at least a crystallized region in a channel region, which is defined as a region of interest (ROI) for a semiconductor device.
Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

1,501 citations

Journal ArticleDOI
TL;DR: In this paper, a direct bandgap GeSn alloy, grown directly onto Si(001), was used for experimentally demonstrating lasing threshold and linewidth narrowing at low temperatures.
Abstract: Lasing is experimentally demonstrated in a direct bandgap GeSn alloy, grown directly onto Si(001). The authors observe a clear lasing threshold as well as linewidth narrowing at low temperatures.

1,027 citations

Patent
16 Feb 2005
TL;DR: In this article, a bypass pipe is connected between the mechanical booster pump and the rest vacuum pumps located at a downstream side of the booster pump to prevent the exhaust gas from diffusing back to the inside of a process chamber.
Abstract: Process gas discharged from a bypass pipe to a gas exhaust system can be prevented from diffusing back to the inside of a process chamber without having to install a dedicated vacuum pump at the downstream side of the bypass pipe. The substrate processing apparatus includes a process chamber accommodating a substrate, a gas supply system supplying process gas from a process gas source to the process chamber for processing the substrate, a gas exhaust system configured to exhaust the process chamber, two or more vacuum pumps installed in series at the gas exhaust system, and a bypass pipe connected between the gas supply system and the gas exhaust system. The most upstream one of the vacuum pumps is a mechanical booster pump, and the bypass pipe is connected between the mechanical booster pump and the rest vacuum pumps located at a downstream side of the mechanical booster pump.

644 citations

Journal ArticleDOI
TL;DR: In this paper, a theoretical model was developed based on the nonlocal empirical pseudopotential method to determine the electronic band structure of germanium tin (GeSn) alloys, and modifications to the virtual crystal potential accounting for disorder induced potential fluctuations were incorporated to reproduce the large direct band gap bowing observed in GeSn alloys.
Abstract: GeSn is predicted to exhibit an indirect to direct band gap transition at alloy Sn composition of 6.5% and biaxial strain effects are investigated in order to further optimize GeSn band structure for optoelectronics and high speed electronic devices. A theoretical model has been developed based on the nonlocal empirical pseudopotential method to determine the electronic band structure of germanium tin (GeSn) alloys. Modifications to the virtual crystal potential accounting for disorder induced potential fluctuations are incorporated to reproduce the large direct band gap bowing observed in GeSn alloys.

368 citations

Patent
23 Sep 2011
TL;DR: In this article, the dopant species is delivered to the film between the cycles of adsorption and reaction in a surface-mediated reaction, where a film is grown over one or more cycles of reaction.
Abstract: Methods of depositing a film on a substrate surface include surface mediated reactions in which a film is grown over one or more cycles of reactant adsorption and reaction. In one aspect, the method is characterized by intermittent delivery of dopant species to the film between the cycles of adsorption and reaction.

341 citations