Yi-Chun Huang

Bio: Yi-Chun Huang is an academic researcher from TSMC. The author has contributed to research in topics: CMOS & Logic gate. The author has an hindex of 4, co-authored 5 publications receiving 170 citations.

High performance 22/20nm FinFET CMOS devices with advanced high-K/metal gate scheme

Abstract: A high performance 22/20nm CMOS bulk FinFET achieves the best in-class N/P I on values of 1200/1100 µA/µm for I off =100nA/µm at 1V. Excellent device electrostatic control is demonstrated for gate length (L gate ) down to 20nm. Dual-Epitaxy and multiple stressors are essential to boost the device performance. Dual workfunction (WF) with an advanced High-K/Metal gate (HK/MG) stack is deployed in an integration-friendly CMOS process flow. This dual-WF approach provides excellent V th roll-off immunity in the short-channel regime that allows properly positioning the long-channel device V th . Enhanced 193nm immersion lithography has enabled the stringent requirements of the 22/20nm ground rules. Reliability of our advanced HK/MG stack is promising. Excellent SRAM static noise margin at 0.45V is reported.

A 65nm node strained SOI technology with slim spacer

Abstract: A 65 nm node strained SOI technology with high performance is demonstrated, providing drive currents of 1015 and 500 /spl mu/A//spl mu/m for N-FET and P-FET, respectively, at an off-state leakage of 40 nA//spl mu/m using 1 V operation The technology employs an aggressively scaled slim spacer of 30 nm width to amplify stress benefits for performance improvement, and to reduce by 10-20 % the layout area for SRAM-cell-like circuits, while maintaining excellent hot carrier immunity and well-controlled short-channel effects For the first time, we demonstrate that FinFET devices, implicitly implemented in this technology, offer a 8-15 % higher inverter speed compared to planar SOI devices at the same drive current

High performance dual-gate ISFET with non-ideal effect reduction schemes in a SOI-CMOS bioelectrical SoC

Abstract: A dual-gate ion-sensitive field-effect transistor (DGFET) with the back-side sensing structure implemented in a 0.18 μm SOI-CMOS SoC platform realizing high performance bioelectrical detection with non-ideal effect reduction is presented. Non-ideal effects of the conventional ISFET, such as time drift and hysteresis, are suppressed by the innovative scheme in DGFET using the bottom poly-gate (PG) transistor instead of the fluidic gate (FG) transistor for sensing. As a result, the signal-to-noise ratio (SNR) is improved by 155x, time drift is reduced by 53x, and hysteresis is reduced by 3.7x. For certain applications which require high sensitivity, a pulse-modulated biasing technique can be adopted to effectively reduce time drift with high pH sensitivity of 453 mV/pH which is ∼7.5x enhancement over the Nernst limit in the proposed DGFET.

Spacer layer etch method providing enhanced microelectronic device performance

Abstract: A method for forming a field effect transistor device employs a conformal spacer layer formed upon a gate electrode. The gate electrode is employed as a mask for forming a lightly doped extension region within the semiconductor substrate and the gate electrode and conformal spacer layer are employed as a mask for forming a source/drain region within the semiconductor substrate. An anisotropically etched shaped spacer material layer is formed upon the conformal spacer layer and isotropically etched to enhance exposure of the source/drain region prior to forming a silicide layer thereupon.

MOS transistor and fabrication method thereof

Abstract: A method for fabricating MOS transistor. The method includes the steps of providing a substrate with a gate structure thereon, and then forming first spacers on the sidewalls thereof. Thereafter, a first ion implantation is carried out using the gate structure and the first spacers as a mask to form lightly doped drain regions in the substrate. Subsequently, second spacers are formed on the exterior sidewalls of the first spacers. Then, a second ion implantation is carried out using the gate structure, the first spacers and the second spacers as a mask to form source/drain regions in the substrate. The first and second spacers are then etched to expose a portion of the vertical sidewalls of the gate and a portion of the substrate adjacent to source/drain regions. The exposed top surfaces of the gate, the exposed portion of the vertical sidewalls of the gate and the exposed source/drain regions are then covered by silicide formed during silicidation. Finally, the remaining metal is removed and the formation of salicide (self-aligned silicide) is completed.

Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors

Abstract: For more than four decades, transistors have been shrinking exponentially in size, and therefore the number of transistors in a single microelectronic chip has been increasing exponentially. Such an increase in packing density was made possible by continually shrinking the metal–oxide–semiconductor field-effect transistor (MOSFET). In the current generation of transistors, the transistor dimensions have shrunk to such an extent that the electrical characteristics of the device can be markedly degraded, making it unlikely that the exponential decrease in transistor size can continue. Recently, however, a new generation of MOSFETs, called multigate transistors, has emerged, and this multigate geometry will allow the continuing enhancement of computer performance into the next decade.

Considerations for Ultimate CMOS Scaling

Abstract: This review paper explores considerations for ultimate CMOS transistor scaling Transistor architectures such as extremely thin silicon-on-insulator and FinFET (and related architectures such as TriGate, Omega-FET, Pi-Gate), as well as nanowire device architectures, are compared and contrasted Key technology challenges (such as advanced gate stacks, mobility, resistance, and capacitance) shared by all of the architectures will be discussed in relation to recent research results

Exploring sub-20nm FinFET design with predictive technology models

Abstract: Predictive MOSFET models are critical for early stage design-technology co-optimization and circuit design research In this work, Predictive Technology Model files for sub-20nm multi-gate transistors have been developed (PTM-MG) Based on MOSFET scaling theory, the 2011 ITRS roadmap and early stage silicon data from published results, PTM for FinFET devices are generated for 5 technology nodes corresponding to the years 2012-2020 on the ITRS roadmap