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Yi-Hsuan Fan

Bio: Yi-Hsuan Fan is an academic researcher from National Sun Yat-sen University. The author has contributed to research in topics: Transistor & MOSFET. The author has an hindex of 3, co-authored 21 publications receiving 33 citations.

Papers
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Journal ArticleDOI
TL;DR: In this article, a block oxide (BO) and source/drain (S/D)-tied structure was proposed for high-performance field effect transistor (FET) devices.
Abstract: In this paper, we present a highly scaled bulk metal-oxide-semiconductor field-effect transistor with block oxide (BO) and source/drain (S/D)-tied structure that meets the International Technology Roadmap for Semiconductors requirements for high-performance devices. This new device requires only a simple BO fabrication process using SiGe-Si epitaxial growth with selective SiGe removal and requires no additional lithography masks. This proposed BO fabrication process is simple due to it being controllable, repeatable, and fully compatible with standard complementary metal-oxide-semiconductor technology. According to 3-D simulations, our proposed structure not only exhibits its structural advantages to overcome scaling obstacles but also extends the use of planar bulk technology to the decananometer regime.

10 citations

Proceedings ArticleDOI
17 Dec 2010
TL;DR: In this paper, the authors proposed a vertical MOSFET with the middle partial insulation and block oxide (bMPI) structure for 1T-DRAM application, which can increase the pseudo-neutral region due to the bMPI under the vertical channel.
Abstract: This paper proposes a novel vertical MOSFET with the middle partial insulation and block oxide (bMPI) structure for 1T-DRAM application. The bMPI 1T-DRAM can increase the pseudo-neutral region due to the bMPI under the vertical channel and its device sensing current window is improved about 95% when compared to the planer bMPI 1T-DRAM. Because of the double gate structure, the proposed device has great gate controllability; hence, it can reduce the short-channel effects and enhance the electrical characteristics.

5 citations

Proceedings ArticleDOI
13 Dec 2010
TL;DR: In this paper, a performance comparison between junction and junctionless thin-film transistors (TFTs) by using TCAD simulations is presented, showing that the DIBL and S.S. of a junctionless TFT (JLTFT) are larger and higher, respectively, than those of its junction TFT counterpart.
Abstract: This paper for the first time presents a performance comparison between junction and junctionless thin-film transistors (TFTs) by using TCAD simulations. Note that the DIBL and S.S. of a junctionless TFT (JLTFT) are larger and higher, respectively, than those of its junction TFT (JTFT) counterpart. Although the JLTFT gets a higher current drive based on the same V ov as compared with the JTFT, its short-channel characteristics are worse and degraded. These results can be attributed to the fact that the major carriers in channel region for a JTFT make itself a barrier to carrier scattering, whereas, the JTFT does not have this problem, leading to get a high current drive. On the other hand, it may be owing to the grain boundary effects for a JLTFT to degrade its short-channel behavior. Fortunately, these results are still acceptable for scaled dimensions of TFTs.

5 citations

Proceedings ArticleDOI
05 Jul 2010
TL;DR: In this article, a source-tied vertical MOSFET (STVMOS) was proposed by using 3D simulation, which achieved 70 mV/decade S.S. and 145mV/V DIBL, and more than 109 I ON/I OFF current ratio.
Abstract: In this paper, we propose a source-tied vertical MOSFET (STVMOS) by using 3-D simulation. The characteristics of STVMOS are not only similar to the SOI vertical MOSFET (SOI-VMOS), but also have much better thermal reliability. According to TCAD simulation results, we have achieved 70 mV/decade S.S., 145 mV/V DIBL, and more than 109 I ON /I OFF current ratio.

3 citations

Proceedings ArticleDOI
17 Dec 2010
TL;DR: The non-traditional CMOS inverter composed of a junctionless (JL) NMOSFET and an N-N-N−-P transistor can be used in the COMS circuit to advance the issues of the conventional CMOS today.
Abstract: We present a non-traditional CMOS inverter composed a junctionless (JL) NMOSFET and an N+-N−-P transistor which with simple process and high integration density in this paper. In the non-traditional CMOS inverter the JL NMOSFET serves as driver and the N+-N−-P transistor serves as load, respectively. Based on the measurement date of the N+-N−-P transistor published, we draw the load line of the non-traditional CMOS inverter and we found out that the N+-N−-P transistor can be used in the COMS circuit to advance the issues of the conventional CMOS today. Besides, the area reduced more than 46.1% are also be achieved.

2 citations


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Journal ArticleDOI
TL;DR: In this article, the characteristics and sensitivities of p-type junctionless gate-all-around (GAA) nanowire transistors are demonstrated by simulating a 3D quantum transport device with a view to their use in CMOS technology.
Abstract: The characteristics and sensitivities of p-type junctionless (JL) gate-all-around (GAA) (JLGAA) nanowire transistors are demonstrated by simulating a 3-D quantum transport device with a view to their use in CMOS technology. The concentration of dopants in a p-type JL nanowire transistor is not as high as that in an n-type device owing to solid solubility of boron in silicon. However, we can use a midgap material as gate electrode to design an appropriate device threshold voltage. The p-type JLGAA transistor exhibits a favorable on/off current ratio and better short-channel characteristics than a conventional inversion-mode transistor with a GAA structure. Sensitivity analyses reveal that the channel thickness and random dopant fluctuation substantially affect the device performance in terms of threshold voltage (Vth), on current (Ion), and subthreshold slope because of the full depletion condition of the channel. The channel length and oxide thickness have less impact because the short-channel effect is well controlled.

41 citations

Journal ArticleDOI
TL;DR: The atomic force microscopy nanolithography with two wet etching processes was implemented to fabricate simple structures as double gate and single gate junctionless silicon nanowire transistor on low doped p-type silicon-on-insulator wafer.
Abstract: The junctionless nanowire transistor is a promising alternative for a new generation of nanotransistors. In this letter the atomic force microscopy nanolithography with two wet etching processes was implemented to fabricate simple structures as double gate and single gate junctionless silicon nanowire transistor on low doped p-type silicon-on-insulator wafer. The etching process was developed and optimized in the present work compared to our previous works. The output, transfer characteristics and drain conductance of both structures were compared. The trend for both devices found to be the same but differences in subthreshold swing, ‘on/off’ ratio, and threshold voltage were observed. The devices are ‘on’ state when performing as the pinch off devices. The positive gate voltage shows pinch off effect, while the negative gate voltage was unable to make a significant effect on drain current. The charge transmission in devices is also investigated in simple model according to a junctionless transistor principal.

30 citations

Journal ArticleDOI
TL;DR: In this paper, a hetero-gate-dielectric double gate junctionless transistor (HGJLT) was proposed to reduce the effects of band-to-band tunnelling in the sub-threshold region.
Abstract: We propose a hetero-gate-dielectric double gate junctionless transistor (HGJLT), taking high-k gate insulator at source side and low-k gate insulator at drain side, which reduces the effects of band-to-band tunnelling (BTBT) in the sub-threshold region. A junctionless transistor (JLT) is turned off by the depletion of carriers in the highly doped thin channel (device layer) which results in a significant band overlap between the valence band of the channel region and the conduction band of the drain region, due to off-state drain bias, that triggers electrons to tunnel from the valence band of the channel region to the conduction band of the drain region leaving behind holes in the channel. These effects of band-to-band tunnelling increase the sub-threshold leakage current, and the accumulation of holes in the channel forms a parasitic bipolar junction transistor (n–p–n BJT for channel JLT) in the lateral direction by the source (emitter), channel (base) and drain (collector) regions in JLT structure in off-state. The proposed HGJLT reduces the subthreshold leakage current and suppresses the parasitic BJT action in off-state by reducing the band-to-band tunnelling probability.

25 citations

Journal ArticleDOI
TL;DR: In this article, the authors proposed metaloxide-semiconductor field effect transistor (MOSFET) types featuring additional L-shaped counterdoped areas in the source and/or drain regions of silicon-on-insulator (SOI) MOSFets to reduce drain-induced barrier lowering (DIBL) through the buried oxide (BOX) layer.
Abstract: In this paper, the authors propose novel metal-oxide-semiconductor field-effect transistor (MOSFET) types featuring additional L-shaped counterdoped areas in the source and/or drain regions of silicon-on-insulator (SOI) MOSFETs to reduce drain-induced barrier lowering (DIBL) through the buried oxide (BOX) layer. The L-shaped region in the drain area shields the BOX layer from penetration by the drain electric field, thereby reducing DIBL in the body region. Simulation of the electrical characteristics of these novel MOSFETs demonstrated more remarkable DIBL suppression and subthreshold slope performance in short-channel regions than in conventional SOI MOSFETs. In addition to this suppression, these novel MOSFETs suppress breakdown voltage more effectively than conventional SOI MOSFETs. The authors concluded that the proposed devices are capable of contributing to the scaling of SOI MOSFETs in ultralarge-scale integration circuits.

23 citations