scispace - formally typeset
Search or ask a question
Author

Yi-Ting Liao

Bio: Yi-Ting Liao is an academic researcher from National Ilan University. The author has contributed to research in topics: Pipeline (computing) & Complex multiplier. The author has an hindex of 1, co-authored 1 publications receiving 62 citations.

Papers
More filters
Journal ArticleDOI
01 Feb 2011
TL;DR: To eliminate the read-only memories used to store the twiddle factors, the proposed architecture applies a reconfigurable complex multiplier and bit-parallel multipliers to achieve a ROM-less FFT/IFFT processor, thus consuming lower power than the existing works.
Abstract: 4G and other wireless systems are currently hot topics of research and development in the communication field. Broadband wireless systems based on orthogonal frequency division multiplexing (OFDM) often require an inverse fast Fourier transform (IFFT) to produce multiple subcarriers. In this paper, we present the efficient implementation of a pipeline FFT/IFFT processor for OFDM applications. Our design adopts a single-path delay feedback style as the proposed hardware architecture. To eliminate the read-only memories (ROM's) used to store the twiddle factors, the proposed architecture applies a reconfigurable complex multiplier and bit-parallel multipliers to achieve a ROM-less FFT/IFFT processor, thus consuming lower power than the existing works. The design spends about 33.6K gates, and its power consumption is about 9.8mW at 20MHz.

67 citations


Cited by
More filters
Journal ArticleDOI
TL;DR: A novel 128/256/512/1024/1536/2048-point single-path delay feedback (SDF) pipeline FFT processor for long-term evolution and mobile worldwide interoperability for microwave access systems and formulated a hardware-sharing mechanism to reduce the memory space requirements of the proposed 1536-point FFT computation scheme.
Abstract: Fast Fourier transform (FFT) is widely used in digital signal processing and telecommunications, particularly in orthogonal frequency division multiplexing systems, to overcome the problems associated with orthogonal subcarriers. This paper presents a novel 128/256/512/1024/1536/2048-point single-path delay feedback (SDF) pipeline FFT processor for long-term evolution and mobile worldwide interoperability for microwave access systems. The proposed design employs a low-cost computation scheme to enable 1536-point FFT, which significantly reduces hardware costs as well as power consumption. In conjunction with the aforementioned 1536-point FFT computation scheme, the proposed design included an efficient three-stage SDF pipeline architecture on which to implement a radix-3 FFT. The new radix-3 SDF pipeline FFT processor simplifies its data flow and is easy to control, and the complexity of the resulting hardware is lower than that of existing structures. This paper also formulated a hardware-sharing mechanism to reduce the memory space requirements of the proposed 1536-point FFT computation scheme. The proposed design was implemented using 90 nm CMOS technology. Postlayout simulation results revealed a die area of approximately $1.44 \times 1.44~\mathrm{mm}^{2}$ with power consumption of only 9.3 mW at 40 MHz.

49 citations

Journal ArticleDOI
TL;DR: This work concentrates on the trivial multiplications in the input stage of the IFFT unit and replaces them by the proposed ‘pass-logic’, and the performance improvements of the proposed FFT/IFFT implementation have been analysed.
Abstract: In an orthogonal frequency division multiplexing (OFDM)-based digital transmitter, the inverse fast Fourier transform (IFFT) processing unit consumes the most hardware area and power, especially because of the twiddle multipliers in the Cooley–Tukey-based decimation-infrequency (DIF) IFFT architecture. This work concentrates on the trivial multiplications in the input stage of the IFFT unit and replaces them by the proposed ‘pass-logic’. These replacements can be possible because the inputs are bitwise with binary-phase shift keying (PSK) or qudrature-PSK digital modulation. The input stage of DIF-FFT for 8 to 128 points (N) were implemented with multipliers and ‘pass-logics’. The performance improvements (PIs) of the proposed FFT/IFFT implementation have been analysed. For a 64-point FFT in FPGA, the number of slices was reduced by 9% and the total power by 6.5%. The same implementation on an ASIC, consumed 28% less power and 27% lesser gates. In 128-point implementation, these PIs are more than those of the 64-point, thus PI is in upward trend as N increases. A chip for FFT processing as per IEEE 802.11a specifications (64-point, 16-bit data) is designed with pass-logics, which uses 24 947 gates and consumes 6.45 mW at 1.8 V, 20 MHz in 0.18 µm 1P6M CMOS process.

26 citations

Book ChapterDOI
01 Jan 2020
TL;DR: In this paper multiplierless radix-2/4 FFT architecture using MBSLS was proposed, but here constant multiplication is replaced by shift and add structure unit and the memory of the twiddle factor is minimized by increasing the computation speed with the help of Winograd Fourier transform algorithm.
Abstract: In modem communications the FFT/IFFT has been normally used in recent years due to its effectiveness in OFDM applications. In this paper multiplierless radix-2/4 FFT architecture using MBSLS was proposed, but here constant multiplication is replaced by shift and add structure unit. The memory of the twiddle factor is minimized by increasing the computation speed with the help of Winograd Fourier transform algorithm. Thus the proposed method offers minimal hardware requirement as well as reduction in complex multiplication in FFT calculation. This method achieves good performance in terms of less area. This architecture has been simulated in Xilinx ISE12.14 software by using Verilog coding and is used in the mobile Wi-MAX application in OFDM.

19 citations

Proceedings ArticleDOI
01 Dec 2013
TL;DR: A Radix-43 based FFT architecture suitable for OFDM based WLAN applications and uses a radix-4 butterfly unit which takes all four inputs in parallel and can selectively produce one out of the four outputs.
Abstract: This paper presents a Radix-43 based FFT architecture suitable for OFDM based WLAN applications. The radix-43 parallel unrolled architecture presented here, uses a radix-4 butterfly unit which takes all four inputs in parallel and can selectively produce one out of the four outputs. A 64 point FFT processor based on the proposed architecture has been implemented in UMC 130nm 1P8M CMOS process with a maximum clock frequency of 100 MHz and area of 0.83mm2. The proposed processor provides a throughput of four times the clock rate and can finish one 64 point FFT computation in 16 clock cycles. For IEEE 802.11a/g WLAN, the processor needs to be operated at a clock rate of 5 MHz with a power consumption of 2.27 mW which is 27% less than the previously reported low power implementations.

13 citations

Journal ArticleDOI
TL;DR: An area-efficient and low power 16-bit word-width 64-point Radix-22 and radix-23 pipelined FFT architectures for an OFDM-based IEEE 802.11a wireless LAN baseband and implementation results show reduction in hardware cost and power consumption.

12 citations