Yie-Gie Liaw

Bio: Yie-Gie Liaw is an academic researcher. The author has contributed to research in topics: NMOS logic & Gate oxide. The author has an hindex of 1, co-authored 1 publications receiving 31 citations.

Investigation of Reliability Characteristics in NMOS and PMOS FinFETs

Abstract: Three-dimensional vertical double-gate (FinFET) devices with a high aspect ratio (Si-fin height/width = Hfin/Wfin = 86 nm/17 nm) and a gate nitrided oxide of 14 Aring thickness have been successfully fabricated. Reliability characterizations, including hot-carrier injection (HCI) for NMOS FinFETs and negative bias temperature instability (NBTI) for PMOS FinFETs, are carried out in order to determine their respective lifetimes. The predicted HCI dc lifetime for a 50-nm gate-length NMOS FinFET device at the normal operating voltage (Vcc) of 1.1 V is 133 years. A wider fin-width (27 nm) PMOS FinFET exhibits promising NBTI lifetime such as 26.84 years operating at Vcc = 1.1 V, whereas lifetime is degraded for a narrower fin-width (17 nm) device that yields 2.76 years of lifetime at the same operating voltage and stress conditions.

A unified aging model of NBTI and HCI degradation towards lifetime reliability management for nanoscale MOSFET circuits

Abstract: As planar MOSFETs is approaching its physical scaling limitation, FinFET becomes one of the most promising alternative structure to keep on the industry scaling-down trend for future technology generations of 22 nm and beyond. In this paper, we propose a unified reliability model of Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) for double-gate and triple-gate FinFETs, towards a practical reliability assessment method for future FinFETs based circuits. The model is based on the reaction-diffusion theory and extends it such that it covers the FinFET specific geometrical structures. Apart of introducing the reliability model we also investigate the circuit performance degradation due to NBTI and HCI in order to create the premises for its utilization for assessing and monitoring the Integrated Circuits (ICs) aging process. To validate our model we simulated NBTI and HCI degradation and compared the obtained V th shift prediction with the one evaluated based on experimental data. The simulations suggest that our model characterize the NBTI and HCI process with accuracy and it is computationally efficient, which makes it suitable for utilization in reliability-aware architectures as reliability prediction/assesment kernel for lifetime reliability management mechanisms.

Effects of Fin Width on Device Performance and Reliability of Double-Gate n-Type FinFETs

Abstract: This paper investigates the impact of fin width ( Wfins = 15, 20, and 25 nm) in a double-gate n-type FinFET on the performance and reliability of the device. Carrier conduction in the Si-fin body of FinFETs with various Wfins is also studied. The experimental results show that the threshold voltage and drain current of n-type FinFETs increases and decreases, respectively, as Wfin is reduced. A thinner Wfin FinFET exhibits greater immunity to short channel effects. In addition, according to the analysis results of low-frequency noise, the thinnest Wfin FinFET possesses the largest bulk oxide trap density (NBOT) than that of a thicker Wfin FinFET. Moreover, the noise of the thinnest Wfin (15 nm) FinFET is largely dominated by the fluctuation of carrier number. In the hot-carrier injection (HCI) reliability test, the thinnest Wfin FinFET shows less performance degradation than those of the thicker ones. However, by removing the effect of the parasitic source/drain resistance, we believe that the volume inversion charged carriers flow through the entire thin Si-fin having a lower surface roughness and Coulomb scattering than those of thicker ones, which results in a higher carrier temperature and worsening of the reliability of the HCI.

Thermal behavior of self-heating effect in FinFET devices acting on back-end interconnects

Abstract: Thermal impact on back-end interconnects resulted from self-heating (SH) effect in FinFET devices is investigated here The self-heating effect in FinFET devices will generate more heat in fin structures than planar devices and influence the reliability of interconnects In this study, testing structures including metal sensors of different metal layers are designed, fabricated and measured, as well as a computer-aided finite element model is also built and utilized in this report With FinFET devices, the evaluation includes temperature saturation with the number of powered devices, temperature rising in different metal layer, and self-heating effect accompanying with joule heating (so-called coupling effect) This investigation shows the contribution of SH effect would change with varying joule heating It is important to considering the temperature rising from SH effect when assess the risk of back-end interconnects reliability

Reliability Modeling and Analysis of Hot-Carrier Degradation in Multiple-Fin SOI n-Channel FinFETs With Self-Heating

Abstract: A comprehensive study on hot-carrier degradation (HCD) mechanisms in 14 nm silicon-on-insulator (SOI) n-channel FinFETs is presented The impact of high-frequency AC stress bias on self-heating (SH) enhanced hot-carrier injection in oxide bulk traps is investigated and compared with the measurement results using the conventional DC stress bias The influence of SH on electrical parameter degradation due to hot-carriers is shown as an important metric for accurate device reliability analysis The relative contribution of bulk and interface traps is determined to identify the dominant mechanism responsible for HCD for different device geometries The device behavior is thoroughly studied under hot-carrier DC and AC stresses for different device design parameters, such as effective oxide thickness, number of fins, and channel length Based on measured data, we have proposed an empirical model for reliability degradation, which takes into account some of the key device design parameters and stress bias frequency