Yinan Wang

Bio: Yinan Wang is an academic researcher from National University of Defense Technology. The author has contributed to research in topics: Computer science & Data acquisition. The author has an hindex of 5, co-authored 34 publications receiving 135 citations. Previous affiliations of Yinan Wang include Linköping University.

Joint Blind Calibration for Mixed Mismatches in Two-Channel Time-Interleaved ADCs

Abstract: To further enhance the dynamic performance of time-interleaved analog-to-digital converters (TI-ADCs), both linear and nonlinear mismatches should be estimated and compensated for. This paper introduces a method for joint calibration of several types of linear and nonlinear mismatch errors in two-channel TI-ADCs. To demonstrate the generality of this method, we take different scenarios into account, including static and dynamic mixed mismatch models. The proposed method utilizes a normalized least-mean square (N-LMS) algorithm as well as a certain low degree of oversampling for the overall converter to estimate and compensate for the mixed mismatch errors. The calibration performance and computational complexity are investigated and evaluated through simulations.

Adaptive Background Estimation for Static Nonlinearity Mismatches in Two-Channel TIADCs

Abstract: Due to channel mismatches in time-interleaved analog-to-digital converters (TIADCs), estimation and compensation methods are required to restore the resolution of the individual converters. Whereas several methods exist for linear mismatches, nonlinearity mismatches have not been widely investigated. This brief presents an adaptive background estimation method for nonlinearity mismatches in two-channel TIADCs. It utilizes a normalized least-mean-square algorithm and assumes slight oversampling as well as a polynomial nonlinearity model that is appropriate when smooth errors dominate. Furthermore, two implementation strategies are proposed to enhance its ability for different applications. The estimation performance of the proposed method is evaluated through behavioral-level simulations.

Energy-Efficient Memristive Euclidean Distance Engine for Brain-Inspired Competitive Learning

Abstract: Inspired by competitive rules of the nature, competitive learning contributes to the specialization of the human brain and the general creativity of mankind. However, the construction of hardware competitive learning neural network still faces great challenges due to the lack of an accurate distance computation method and a self‐adaptive in situ training scheme. Herein, a fully memristive Euclidean distance (ED) engine based on analog multiply‐accumulate operation in a 32 × 32 TiN/TaO x /HfO x /TiN 1T1R array is demonstrated. The dual‐layer devices perform multilevel modulation under the target‐aware programming method with excellent read linearity in a dynamic range of 10–100 μS. The ED calculation is verified experimentally on a test board with an O(1) temporal complexity. Furthermore, in situ training and offline inference schemes for competitive learning, based on the ED engine, are developed and the simulated results show comparable success rates with those obtained by the CPU‐based software. Compared with a state‐of‐the‐art RTX6000 GPU (0.5 TOPS W−1), the energy efficiency of competitive learning models on ED engines can yield 100× improvements by utilizing optimized memristive devices.

Estimation method for nonlinearity mismatch in time-interleaved analog-to-digital converters

Abstract: Channel mismatches of time-interleaved analog-to-digital converters (TIADC) would result in significant decline of dynamic performance, especially in signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR). However, as one kind of the channel mismatches, nonlinearity mismatch has not been widely investigated. In this paper, we analyze the characteristics of nonlinearity mismatch and its influence on TIADC's dynamic performance by using polynomial model. A foreground estimation method is proposed and evaluated. The simulation results demonstrate that the proposed method can perform fine estimation accuracy. Furthermore, we investigate the relationship between the estimation accuracy and the sample length, and the result is helpful to configure an appropriate sample length according to different performance requirements.

Recent Developments and Challenges in FPGA-Based Time-to-Digital Converters

Abstract: Over the past few years, the gap between field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) performance levels has been narrowed due to the constant development of FPGA technology. The high performance, together with the lower development costs and a shorter time to market, turns FPGA-based platforms attractive for a huge range of applications, among them time-to-digital converters (TDCs). It is, therefore, important to analyze the evolution of FPGA-based TDCs to better understand where the research efforts should be focused in the near future. This article presents and discusses the improvements on the FPGA-based TDC research, aiming to be a starting point for new studies on this field, with some guidelines for future research. A state-of-the-art literature review on the FPGA-based TDC is presented, aiming to categorize and discuss the existing architectures. This discussion addresses architectures’ characteristics, limitations, and areas of application.

Joint Blind Calibration for Mixed Mismatches in Two-Channel Time-Interleaved ADCs

Abstract: To further enhance the dynamic performance of time-interleaved analog-to-digital converters (TI-ADCs), both linear and nonlinear mismatches should be estimated and compensated for. This paper introduces a method for joint calibration of several types of linear and nonlinear mismatch errors in two-channel TI-ADCs. To demonstrate the generality of this method, we take different scenarios into account, including static and dynamic mixed mismatch models. The proposed method utilizes a normalized least-mean square (N-LMS) algorithm as well as a certain low degree of oversampling for the overall converter to estimate and compensate for the mixed mismatch errors. The calibration performance and computational complexity are investigated and evaluated through simulations.

A High-Precision Time Skew Estimation and Correction Technique for Time-Interleaved ADCs

Abstract: This paper presents an all-digital background calibration technique for the time skew mismatch in time-interleaved ADCs (TIADCs). The technique jointly estimates all of the time skew values by processing the outputs of a bank of correlators. A low-complexity sampling sequence intervention technique, suitable for successive approximation register (SAR) ADC architectures, is proposed to overcome the limitations associated with blind estimation. A two-stage digital correction mechanism based on the Taylor series is proposed to satisfy the target high-precision correction. A quantitative study is performed regarding the requirements imposed on the digital correction circuit in order to satisfy the target performance and yield, and a corresponding filter design method is proposed, which is tailored to meet these requirements. Mitchell’s logarithmic multiplier is adopted for the implementation of the principal multipliers in both the estimation and correction mechanisms, leading to a 25% area and power reduction in the estimation circuit. The proposed calibration is synthesized using a TSMC 28-nm HPL process targeting a 2.4-GHz sampling frequency for an eight-sub-ADC system. The calibration block occupies 0.03 mm2 and consumes 11 mW. The algorithm maintains the SNDR above 65 dB for a sinusoidal input within the target bandwidth.

Review of Analog-To-Digital Conversion Characteristics and Design Considerations for the Creation of Power-Efficient Hybrid Data Converters

Abstract: This article reviews design challenges for low-power CMOS high-speed analog-to-digital converters (ADCs). Basic ADC converter architectures (flash ADCs, interpolating and folding ADCs, subranging and two-step ADCs, pipelined ADCs, successive approximation ADCs) are described with particular focus on their suitability for the construction of power-efficient hybrid ADCs. The overview includes discussions of channel offsets and gain mismatches, timing skews, channel bandwidth mismatches, and other considerations for low-power hybrid ADC design. As an example, a hybrid ADC architecture is introduced for applications requiring 1 GS/s with 6–8 bit resolution and power consumption below 11 mW. The hybrid ADC was fabricated in 130-nm CMOS technology, and has a subranging architecture with a 3-bit flash ADC as a first stage, and a 5-bit four-channel time-interleaved comparator-based asynchronous binary search (CABS) ADC as a second stage. Testing considerations and chip measurements results are summarized to demonstrate its low-power characteristics.