Yogendra Sahu

Bio: Yogendra Sahu is an academic researcher from Indian Institute of Technology Kanpur. The author has contributed to research in topics: Flicker noise & Noise (electronics). The author has an hindex of 2, co-authored 2 publications receiving 25 citations.

Compact Modeling of Drain Current Thermal Noise in FDSOI MOSFETs Including Back-Bias Effect

Abstract: In this paper, we present an analytical charge-based model for thermal noise power spectral density in fully depleted silicon on insulator (FDSOI) MOSFETs. Two important aspects particular to FDSOI technology, namely, different inversion charges and different effective mobilities at front and back interfaces, are considered in the model. Proposed model is valid from weak to strong inversion regions of operation. Velocity saturation and channel length modulation are also incorporated to properly capture the excess noise in deep submicrometer MOSFETs. To test the quality of the model, standard benchmark tests are performed and asymptotic behavior of the model is validated in all regions of operation. The model is implemented in SPICE and validated with calibrated TCAD simulations as well as with experimental data of high frequency noise for wide range of back biases.

Characterization of RF Noise in UTBB FD-SOI MOSFET

Abstract: In this paper, we report the noise measurements in the RF frequency range for ultrathin body and thin buried oxide fully depleted silicon on insulator (FD-SOI) transistors. We analyze the impact of back and front gate biases on the various noise parameters; along with discussions on the secondary effects in FD-SOI transistors which contribute to the thermal noise. Using calibrated TCAD simulations, we show that the noise figure changes with the substrate doping and buried oxide thickness.

Autonomous 2-D Near Field Measurements of EOS-04 Phased Array Antenna

Abstract: In this paper, we present an automated test set- up for 2-D near-field data acquisition of EOS-04 6m X 2m phased array antenna. We demonstrate how the automated positioning of the probe antenna in 2-D raster scan was achieved covering all the desired grid points and the corresponding data acquisition at each such position. Using this automation, 2-D near field transmit and receive mode imaging data was acquired to generate far-field patterns via holographic back projection technique.

Time-Efficient Comnutation of EOS-04 Cross-Polarization Imbalance

Abstract: Measurement of Cross-Polarization Imbalance (CPI) of the phased array antenna is a critical step during SAR payload characterization. In this paper, we demonstrate a time-efficient measurement scheme of H-V CPI for EOS-04 antenna via single 2-D raster-scan near-field measurements. The set-up utilizes full-polarization mode of EOS-04 payload and a dual polarized probe for this purpose.

Design and Characterization of a Multiband Polarimetric Active Radar Calibrator at L, S, C and X Band

Abstract: With recent developments of SAR sensors in multiple frequency bands by different space agencies, their accurate calibration is becoming equally important before SAR data can be applied to generate final application product. Active and passive radar calibrators are often used in conjunction with airborne and spaceborne Polarimetric SAR acting as ground based calibration targets with specified RCS. ARC's provide a clear advantage against their Passive counterpart in the fact that their Scattering matrix can be accurately known by design and also for the same RCS it is much smaller than a Corner Reflector. This paper describes the design and Characterization of a Wideband Active Radar calibrator, which can operate in the L, S, C and X bands. Laboratory and field measurements are performed to characterize the performance of the developed ARC for establishing its RCS stability, settability and dynamic range, as well as to evaluate its integrated impulse response. Characterization methodology for lab testing of ARC in Full Polarization mode is also presented. This development has been tested in calibration campaigns for ISRO's EOS-04 SAR and later will be used for calibration of NISAR etc.

Compact Modeling of Drain Current Thermal Noise in FDSOI MOSFETs Including Back-Bias Effect

Abstract: In this paper, we present an analytical charge-based model for thermal noise power spectral density in fully depleted silicon on insulator (FDSOI) MOSFETs. Two important aspects particular to FDSOI technology, namely, different inversion charges and different effective mobilities at front and back interfaces, are considered in the model. Proposed model is valid from weak to strong inversion regions of operation. Velocity saturation and channel length modulation are also incorporated to properly capture the excess noise in deep submicrometer MOSFETs. To test the quality of the model, standard benchmark tests are performed and asymptotic behavior of the model is validated in all regions of operation. The model is implemented in SPICE and validated with calibrated TCAD simulations as well as with experimental data of high frequency noise for wide range of back biases.

Modeling of Back-Gate Effects on Gate-Induced Drain Leakage and Gate Currents in UTB SOI MOSFETs

Abstract: The back-gate bias-dependent gate-induced drain leakage (GIDL) and gate current models of ultrathin body (UTB) silicon-on-insulator (SOI) MOSFETs are proposed. From the experimental data, the GIDL current depends on the back bias due to the electric field change in the channel/drain junction. This effect is modeled using effective gate bias as the threshold voltage shifts. The back-gate bias-dependent gate current is also analyzed and modeled. The voltage across the oxide and available charges for tunneling are the important factors. In accumulation bias condition, the gate leakage is mainly flowing through the overlap region, while in inversion bias condition the current is tunneling from the gate to the channel. Both back bias-dependent GIDL and gate current models are implemented into industry standard compact model Berkeley Short-channel IGFET Model-Independent Multi-Gate for UTB SOI transistors. The model is in good agreement with the experimental data.

Modeling of Advanced RF Bulk FinFETs

Abstract: The modeling of the advanced RF bulk FinFETs is presented in this letter. Extensive S-parameter measurements, performed on the advanced RF bulk FinFETs, show 31% improvement in cutoff frequency over recent work [1] . The transistor’s characteristics are dominated by substrate parasitics at intermediate frequencies (0.1–10 GHz) and gate parasitics at high frequencies (above 10 GHz). The Berkeley short-channel IGFET model-common multi gate model is improved to account for the impact of substrate coupling on the RF parameters. The model demonstrates excellent agreement with the measured data over a broad range of frequencies. The model passes AC, DC and RF symmetry tests, demonstrating its readiness for (RF) circuit design using FinFETs.

Design and Characterization of Ferroelectric Negative Capacitance

Abstract: Author(s): Chatterjee, Korok | Advisor(s): Salahuddin, Sayeef | Abstract: Because of the thermal distribution of electrons in a semiconductor, modern transistors cannot be turned on more sharply than 60 mV of gate voltage for an order of magnitude increase in drain current, the so-called ”Boltzmann tyranny.” This results in an inability to reduce supply voltage, increasing power dissipation in advanced complementary metal- oxide-semiconductor (CMOS) technologies, which threatens the continuation of exponential transistor scaling, also known as Moore’s Law. For this reason, there has been a push in the device research community to invent novel steep swing devices. Negative capacitance in ferroelectric materials was proposed in 2008 by Salahuddin and Datta to provide voltage amplification without needing to design a totally new device. A negative gate capacitance would step-up the applied gate voltage at the semiconductor channel, causing the surface potential to rise faster than the gate voltage, lowering the subthreshold slope below 60 mV/decade. In this work, we attempt to characterize the charge-voltage characteristics of ferroelectrics biased into the negative capacitance regime. Although negative capacitance was experimentally demonstrated in 2010, significant challenges have remained to the practical realization of negative capacitance field-effect transistors (FETs).First, we investigate negative capacitance in an isolated ferroelectric capacitor, and show that the negative capacitance states can be directly observed during switching. Careful analysis of the switching dynamics and phase-field modeling show that the signature of negative capacitance arises from the accelerating growth of domain walls, when an increasing volume fraction of the ferroelectric is depolarized. Although this offers insight into the origins of negative capacitance and help to establish its existence scientifically, it does not address the problem of design. A primary concern is the speed of polarization response, which should be on the order of 1 picosecond or less in order to maintain circuit performance. By analyzing the electromagnetic absorption spectrum of hafnium oxide, the primary candidate for CMOS integration, we are able to estimate the intrinsic delay time as being on the order of 270 fs. Next, in order to maximize the amplification and provide adequate margins for hysteresis-free operation, it is necessary to understand how coupling of the ferroelectric material to the interfacial oxide and semiconductor affects its behavior, and to be able to predict what values of negative capacitance will be realized for a certain material and geometry. This is the problem of capacitance matching, which we aim to solve by using the underlying transistor itself as a charge sensor. By calibrating the drain current to the surface potential in reference devices, we may ascertain the characteristics of the ferroelectric in the negative capacitance devices. This is first carried out with an epitaxial ferroelectric capacitor externally connected to the gate of pre-fabricated Fin-FETs. Following this, we describe the development of an in-house fabrication process using silicon-on-insulator substrates, which allows for simple and efficient process flows. Then, we describe the characterization of these devices, including quasistatic and low-frequency current-voltage (I-V) and capacitance voltage (C-V) measurements, a fast pulse-gated I-V measurement, and an excursion into the memory characteristics of our fabricated FETs. Finally, we discuss efforts to build a computational model of our devices from which we can extract the ferroelectric characteristics needed for predictive design.

Thermal Noise Models for Trigate Junctionless Transistors Including Substrate Bias Effects

Abstract: Thermal noise power spectral density (PSD) models for trigate junctionless field-effect transistors (TG-JLFETs) incorporating substrate bias effects are developed in this article. The PSDs of drain current thermal noise, induced gate noise, and cross correlation between the two noises are derived for TG-JLFET using the modified Klaassen and Prins (KP) equation. An all-region drain current model of TG-JLFET is used to obtain the aforementioned thermal noises. Thermal noise PSD in TG-JLFET depends on channel conductance, and substrate bias voltage significantly modulates the channel conductance, and thus, the substantial impact of substrate bias can be observed on thermal noise of TG-JLFET. Model results are validated with the simulation results obtained using a 3-D technology computer-aided design (TCAD)-based device simulator from Synopsys.