scispace - formally typeset
Search or ask a question
Author

Yong Liu

Bio: Yong Liu is an academic researcher from IBM. The author has contributed to research in topics: CMOS & Low-power electronics. The author has an hindex of 21, co-authored 54 publications receiving 2032 citations. Previous affiliations of Yong Liu include Tsinghua University & Harvard University.


Papers
More filters
Proceedings ArticleDOI
20 Oct 2011
TL;DR: A new architecture is proposed to overcome scalable learning algorithms for networks of spiking neurons in silicon by combining innovations in computation, memory, and communication to leverage robust digital neuron circuits and novel transposable SRAM arrays.
Abstract: Efforts to achieve the long-standing dream of realizing scalable learning algorithms for networks of spiking neurons in silicon have been hampered by (a) the limited scalability of analog neuron circuits; (b) the enormous area overhead of learning circuits, which grows with the number of synapses; and (c) the need to implement all inter-neuron communication via off-chip address-events. In this work, a new architecture is proposed to overcome these challenges by combining innovations in computation, memory, and communication, respectively, to leverage (a) robust digital neuron circuits; (b) novel transposable SRAM arrays that share learning circuits, which grow only with the number of neurons; and (c) crossbar fan-out for efficient on-chip inter-neuron communication. Through tight integration of memory (synapses) and computation (neurons), a highly configurable chip comprising 256 neurons and 64K binary synapses with on-chip learning based on spike-timing dependent plasticity is demonstrated in 45nm SOI-CMOS. Near-threshold, event-driven operation at 0.53V is demonstrated to maximize power efficiency for real-time pattern classification, recognition, and associative memory tasks. Future scalable systems built from the foundation provided by this work will open up possibilities for ubiquitous ultra-dense, ultra-low power brain-like cognitive computers.

345 citations

Journal ArticleDOI
TL;DR: It is shown that neuromorphic systems based on new nanoscale devices can potentially improve density and power consumption by at least a factor of 10, as compared with conventional CMOS implementations.
Abstract: The goal of neuromorphic engineering is to build electronic systems that mimic the ability of the brain to perform fuzzy, fault-tolerant, and stochastic computation, without sacrificing either its space or power efficiency. In this paper, we determine the operating characteristics of novel nanoscale devices that could be used to fabricate such systems. We also compare the performance metrics of a million neuron learning system based on these nanoscale devices with an equivalent implementation that is entirely based on end-of-scaling digital CMOS technology and determine the technology targets to be satisfied by these new devices. We show that neuromorphic systems based on new nanoscale devices can potentially improve density and power consumption by at least a factor of 10, as compared with conventional CMOS implementations.

179 citations

Journal ArticleDOI
TL;DR: Combining microelectronics and microfluidics, the CMOS/microfluidic hybrid system presents a new model for a cell manipulation platform in biological and biomedical applications.
Abstract: Manipulation of biological cells using a CMOS/microfluidic hybrid system is demonstrated. The hybrid system starts with a custom-designed CMOS (complementary metal-oxide semiconductor) chip fabricated in a semiconductor foundry. A microfluidic channel is post-fabricated on top of the CMOS chip to provide biocompatible environments. The motion of individual biological cells that are tagged with magnetic beads is directly controlled by the CMOS chip that generates microscopic magnetic field patterns using an on-chip array of micro-electromagnets. Furthermore, the CMOS chip allows high-speed and programmable reconfiguration of the magnetic fields, substantially increasing the manipulation capability of the hybrid system. Extending from previous work that verified the concept of the hybrid system, this paper reports a set of manipulation experiments with biological cells, which further confirms the advantage of the hybrid approach. To enhance the biocompatibility of the system, the microfluidic channel is redesigned and the temperature of the device is monitored by on-chip sensors. Combining microelectronics and microfluidics, the CMOS/microfluidic hybrid system presents a new model for a cell manipulation platform in biological and biomedical applications.

163 citations

Journal ArticleDOI
29 May 2009
TL;DR: A compact and power-efficient serial I/O targeting dense silicon carrier interconnects is reported, which features low-impedance transmitter termination, high-IMpedance receiver termination, and a receiver with modified DFE with IIR filter feedback (DFE-IIR).
Abstract: The design of compact low-power I/O transceivers continues to be a challenge for both chip-to-chip and backplane applications. The introduction of dense fine-pitch silicon packaging technologies, that in principle are capable of supporting tens of thousands of high-data-rate I/O for local chip-to-chip interconnect, will make I/O area and power requirements even more stringent. Figure 10.2.1 depicts two chips mounted on a silicon (Si) carrier [1], an example of such a dense packaging technology, and connected by fine-pitch interconnects. Characteristics of an example 20mm Si carrier channel are shown in Fig. 10.2.1, showing significant (∼6dB) DC attenuation as well as 17dB of loss at 5GHz. In the time domain, the response to an isolated ‘1’ applied at 10Gb/s shows many postcursors. A DFE would require many taps to be effective, however, the power and area penalty would be prohibitive in this context. This paper describes an alternative low-power compact I/O transceiver with RX equalization that achieves the required multi-bit postcursor cancellation without a high tap-count DFE. While this work targets data transmission over Si carrier links at rates up to 10Gb/s, it is also relevant to backplane channels.

132 citations

Patent
Donhee Ham1, Robert M. Westervelt1, Thomas Hunt1, Yong Liu1, Hakho Lee1 
13 Apr 2005
TL;DR: In this paper, various components relating to the generation of electric and/or magnetic fields are implemented on an IC chip that is fabricated using standard protocols, and the generated electric and or magnetic fields were used to manipulate and or detect one or more dielectric and magnetic particles and distinguish different types of particles.
Abstract: Methods and apparatus for manipulation, detection, imaging, characterization, sorting and/or assembly of biological or other materials, involving an integration of CMOS or other semiconductor-based technology and microfluidics. In one implementation, various components relating to the generation of electric and/or magnetic fields are implemented on an IC chip that is fabricated using standard protocols. The generated electric and/or magnetic fields are used to manipulate and/or detect one or more dielectric and/or magnetic particles and distinguish different types of particles. A microfluidic system is fabricated either directly on top of the IC chip, or as a separate entity that is then appropriately bonded to the IC chip, to facilitate the introduction and removal of cells in a biocompatible environment, or other particles/objects of interest suspended in a fluid. The patterned electric and/or magnetic fields generated by the IC chip can trap and move biological cells or other objects inside the microfluidic system. Electric and/or magnetic field generating components also may be controlled using signals of various frequencies so as to detect one or more cells, particles or objects of interest, and even the type of particle or object of interest, by measuring resonance characteristics associated with interactions between samples and one or more of the field-generating devices. Such systems may be employed in a variety of biological and medical related applications, including cell sorting and tissue assembly.

109 citations


Cited by
More filters
Journal ArticleDOI
TL;DR: Loihi is a 60-mm2 chip fabricated in Intels 14-nm process that advances the state-of-the-art modeling of spiking neural networks in silicon, and can solve LASSO optimization problems with over three orders of magnitude superior energy-delay-product compared to conventional solvers running on a CPU iso-process/voltage/area.
Abstract: Loihi is a 60-mm2 chip fabricated in Intels 14-nm process that advances the state-of-the-art modeling of spiking neural networks in silicon. It integrates a wide range of novel features for the field, such as hierarchical connectivity, dendritic compartments, synaptic delays, and, most importantly, programmable synaptic learning rules. Running a spiking convolutional form of the Locally Competitive Algorithm, Loihi can solve LASSO optimization problems with over three orders of magnitude superior energy-delay-product compared to conventional solvers running on a CPU iso-process/voltage/area. This provides an unambiguous example of spike-based computation, outperforming all known conventional solutions.

2,331 citations

Journal ArticleDOI
18 Jun 2016
TL;DR: This work proposes a novel PIM architecture, called PRIME, to accelerate NN applications in ReRAM based main memory, and distinguishes itself from prior work on NN acceleration, with significant performance improvement and energy saving.
Abstract: Processing-in-memory (PIM) is a promising solution to address the "memory wall" challenges for future computer systems. Prior proposed PIM architectures put additional computation logic in or near memory. The emerging metal-oxide resistive random access memory (ReRAM) has showed its potential to be used for main memory. Moreover, with its crossbar array structure, ReRAM can perform matrix-vector multiplication efficiently, and has been widely studied to accelerate neural network (NN) applications. In this work, we propose a novel PIM architecture, called PRIME, to accelerate NN applications in ReRAM based main memory. In PRIME, a portion of ReRAM crossbar arrays can be configured as accelerators for NN applications or as normal memory for a larger memory space. We provide microarchitecture and circuit designs to enable the morphable functions with an insignificant area overhead. We also design a software/hardware interface for software developers to implement various NNs on PRIME. Benefiting from both the PIM architecture and the efficiency of using ReRAM for NN computation, PRIME distinguishes itself from prior work on NN acceleration, with significant performance improvement and energy saving. Our experimental results show that, compared with a state-of-the-art neural processing unit design, PRIME improves the performance by ~2360× and the energy consumption by ~895×, across the evaluated machine learning benchmarks.

1,197 citations

Journal ArticleDOI
TL;DR: In this paper, the recent progress of synaptic electronics is reviewed, with a focus on the use of synaptic devices for neuromorphic or brain-inspired computing.
Abstract: In this paper, the recent progress of synaptic electronics is reviewed. The basics of biological synaptic plasticity and learning are described. The material properties and electrical switching characteristics of a variety of synaptic devices are discussed, with a focus on the use of synaptic devices for neuromorphic or brain-inspired computing. Performance metrics desirable for large-scale implementations of synaptic devices are illustrated. A review of recent work on targeted computing applications with synaptic devices is presented.

993 citations

Journal ArticleDOI
27 Nov 2019-Nature
TL;DR: An overview of the developments in neuromorphic computing for both algorithms and hardware is provided and the fundamentals of learning and hardware frameworks are highlighted, with emphasis on algorithm–hardware codesign.
Abstract: Guided by brain-like ‘spiking’ computational frameworks, neuromorphic computing—brain-inspired computing for machine intelligence—promises to realize artificial intelligence while reducing the energy requirements of computing platforms. This interdisciplinary field began with the implementation of silicon circuits for biological neural routines, but has evolved to encompass the hardware implementation of algorithms with spike-based encoding and event-driven representations. Here we provide an overview of the developments in neuromorphic computing for both algorithms and hardware and highlight the fundamentals of learning and hardware frameworks. We discuss the main challenges and the future prospects of neuromorphic computing, with emphasis on algorithm–hardware codesign. The authors review the advantages and future prospects of neuromorphic computing, a multidisciplinary engineering concept for energy-efficient artificial intelligence with brain-inspired functionality.

877 citations

Journal ArticleDOI
02 Jan 2017
TL;DR: The relevant virtues and limitations of these devices are assessed, in terms of properties such as conductance dynamic range, (non)linearity and (a)symmetry of conductance response, retention, endurance, required switching power, and device variability.
Abstract: Dense crossbar arrays of non-volatile memory (NVM) devices represent one possible path for implementing massively-parallel and highly energy-efficient neuromorphic computing systems. We first revie...

800 citations