Yoon Hwee Leow

Bio: Yoon Hwee Leow is an academic researcher from Nanyang Technological University. The author has contributed to research in topics: Delta-sigma modulation & Jitter. The author has an hindex of 2, co-authored 3 publications receiving 30 citations.

A 1 V 103 dB 3rd-Order Audio Continuous-Time $\Delta \Sigma $ ADC With Enhanced Noise Shaping in 65 nm CMOS

Abstract: As technology scales, integrating high resolution ADCs into high fidelity mixed signal systems becomes challenging in advanced CMOS processes. Cascading integrators to achieve high-order filter structures limits the modulation index and compromises on stability at the expense of added hardware and power consumption. To optimize the maximum stable amplitude (MSA) to accommodate a larger input dynamic range, the supply rails have to be expanded, which limited technology choices to those of a larger feature size. This work proposes a 25 kHz 3rd-order continuous-time $\Delta \Sigma $ modulator (CT $\Delta \Sigma \text {M}$ ) utilizing a 5-bit SAR quantizer, enabling noise coupling (NC) to be possible in a typical nanoscale CMOS 65 nm technology with VDD of 1 V. Mismatches in SAR comparator and DAC array are mitigated with a proposed calibration scheme while CM mismatches are solved by a floating differential charge storage capacitor (FDCSC) coupling method. To allow sufficient time for SAR bit cycling and noise charge feedback settling, 1 Ts excess loop delay (ELD) is compensated with digital differentiation that minimizes both the power and complexity of the auxiliary feedback DAC. The prototype obtained DR/SNR/SNDR of 103.1 dB/100.1 dB/95.2 dB while dissipating 0.8 mW, hence achieving a FoMSNDR and FoMschreier of 0.34 pJ/level and 177.9 dB, respectively.

A circuit based behavioral modeling of Continuous-Time Sigma Delta modulators

Abstract: In evaluating Continuous-Time Sigma Delta (ΣΔ) Modulators, the generation of highly accurate results requires long simulation time due to the nonlinear nature of the system. In most cases, a compromise has to be made to trade off precision for speed [2]. This paper presents a circuit-based high level model implemented in the MATLAB SIMULINK environment so as to achieve a faster speed of simulation. Designed in a differential manner, the model provides good visualization of the actual circuit at the early stage of design. To maintain simulation accuracy, circuit nonidealities such as system clock jitter, integrator noise, opamp finite gain, bandwidth and slew rate as well as the digital to analog converter (DAC) mismatches are included in the model. For demonstration purpose, a 4th order CT ΣΔ modulator with NRZ (Non-Return to Zero) architecture is implemented. With the proposed models, key design specifications for the functional building blocks are derived.

A high speed tracking quantizer for Continuous-Time multi-bit sigma delta modulators

Abstract: Multi-bit feedback has been conventionally adopted for the implementation of high performance Continuous Time Sigma Delta modulators (CTSDMs) for relaxing multiple design requirements for the system. The need for speed has rendered a large portion of the power budget to be assigned to the quantizer comparators, which often is implemented with the flash architecture. Previous researches [1–3] had proposed the concept of a tracking quantizer to reduce the number of comparators but are primarily more suited for low speed applications. In this paper, a novel technique to implement the tracking capability for high speed is presented. The simplicity of the proposed circuit results in good speed performance with power reduction to the overall multi-bit quantizer design.

A Dynamic Zoom ADC With 109-dB DR for Audio Applications

Abstract: This paper presents the first dynamic zoom ADC. Intended for audio applications, it achieves 109-dB DR, 106-dB signal-to-noise ratio, and 103-dB SNDR in a 20-kHz bandwidth, while dissipating only 1.12 mW. This translates into the state-of-the-art energy efficiency as expressed by a Schreier FoM of 181.5 dB. It also achieves the state-of-the-art area efficiency, occupying only 0.16 mm2 in the 0.16- $\mu \text{m}$ CMOS. These advances are enabled by the use of concurrent fine and coarse conversions, dynamic error-correction techniques, and a dynamically biased inverter-based operational transconductance amplifier.

Analysis and Design of Continuous-Time Delta–Sigma Converters Incorporating Chopping

Abstract: Chopping the operational transconductance amplifier (OTA) of the input integrator in a CT $\Delta \Sigma \text{M}$ is a traditional and effective way of addressing flicker noise in such modulators. Unfortunately, chopping leads to aliasing of shaped quantization noise into the signal band and degrades performance. We analyze the mechanisms of shaped-noise aliasing in OTA- $RC$ integrators that use two-stage feedforward-compensated OTAs, and show that aliasing can be largely mitigated by using an finite impulse response feedback digital-to-analog converter with its zeros placed at multiples of twice the chopping frequency. The theory is borne out by measurement results from a single-bit CT $\Delta \Sigma \text{M}$ , which achieves a peak SNDR of 98.5 dB in a 24-kHz bandwidth while consuming only 280 $\mu \text{W}$ from a 1.8-V supply. Realized in a 180-nm CMOS technology, it achieves a $1/f$ noise corner of about 3 Hz when chopped at $f_{s}/24$ .

A 15.2-ENOB 5-kHz BW 4.5- $\mu$ W Chopped CT $\Delta\Sigma$ -ADC for Artifact-Tolerant Neural Recording Front Ends

Abstract: Implantable closed-loop neural stimulation is desirable for clinical translation and basic neuroscience research. Neural stimulation generates large artifacts at the recording sites, which saturate existing recording front ends. This paper presents a low-power continuous-time delta-sigma analog to digital converter (ADC), which along with an 8 $\times $ gain capacitively-coupled chopper instrumentation amplifier (CCIA), realizes a front end that can digitize neural signals from 1 Hz to 5 kHz in the presence of 200-mVpp differential artifacts and 700-mVpp common-mode (CM) artifacts. A modified loop-filter is used in the ADC along with new linearization techniques to significantly reduce power consumption. Fabricated in 40-nm CMOS, the ADC occupies an area of 0.053 mm2, consumes 4.5 $\mu \text{W}$ from a 1.2-V supply, has an input impedance of 20 $\text{M}\Omega $ and bandwidth (BW) of 5 kHz, and achieves a peak signal to noise and distortion ratio (SNDR) of 93.5 dB for a 1.77- $\text{V}_{\mathrm {pp}}$ differential input at 1 kHz. The ADC’s figure of merit (FOM) (using SNDR) is 184 dB, which is 6 dB higher than the state of the art in high-resolution ADCs. The complete front end occupies an area of 0.113 mm2, consumes 7.3 $\mu \text{W}$ from a 1.2-V supply, has a dc input impedance of 1.5 $\text{G}\Omega $ , input-referred noise of 6.35 $\mu \text{V}_{\mathrm {rms}}$ in 1 Hz–5 kHz, and total harmonic distortion of −81 dB for a 200-mVpp input at 1 kHz, and is immune to 700-mVpp CM interference. Compared to front ends intended for closed-loop neural recording, this paper improves the linear input range by 2 $\times $ , the signal BW by 10 $\times $ , the dynamic range by 12.6 dB, the FOM by 12.4 dB and remains immune to large CM interference while maintaining comparable power, area, and noise performance.

A Continuous-Time Zoom ADC for Low-Power Audio Applications

Abstract: This article presents a continuous-time zoom analog to digital converter (ADC) for audio applications. It employs a high-speed asynchronous SAR ADC that dynamically updates the references of a continuous-time delta–sigma modulator (CTDSM). Compared to previous switched-capacitor (SC) zoom ADCs, its input impedance is essentially resistive, which relaxes the power dissipation of its reference and input buffers. Fabricated in a 160-nm CMOS process, the ADC occupies 0.27 mm2 and achieves 108.1-dB peak SNR, 106.4-dB peak signal to noise and distortion ratio (SNDR), and 108.5-dB dynamic range in a 20-kHz bandwidth while consuming 618 $\mu \text{W}$ . This results in a Schreier figure of merit (FoM) of 183.6 dB.

Analysis and Design of Low-Power Continuous-Time Delta-Sigma Modulator Using Negative-R Assisted Integrator

Abstract: The opamp in the integrators of a continuous-time delta-sigma modulator (CTDSM) has stringent noise and linearity requirements, which lead to large power dissipation. In this paper, a negative-R assisted integrator is proposed to mitigate the opamp’s requirements including dc gain, unity gain bandwidth, thermal and 1/ ${f}$ noise, and linearity, thus enabling a drastic power reduction. We present two prototype CTDSMs using the negative-R assisted integrators that employ a single-bit and tri-level feedback digital-to-analog converter (DAC), respectively. The prototype CTDSMs were fabricated in 65-nm CMOS technology. The first CTDSM using a single-bit feedback DAC achieves dynamic range (DR)/signal to noise and distortion ratio (SNDR)/spurious-free dynamic range (SFDR) of 93.1/88.5/100.5 dB in a 20-kHz bandwidth while dissipating only 55 $\mu \text{W}$ from a 1.2-V supply. The second CTDSM, with a tri-level feedback DAC, achieves DR/SNDR/SFDR of 98.2/94.1/107 dB in a 24-kHz bandwidth while dissipating only 68 $\mu \text{W}$ from a 1.2-V supply. The figures of merit of the two CTDSMs are 178.7 and 183.6 dB, respectively, which are the best energy efficiency among state-of-the-art works.