MOSFETs with gate length down to 17 nm are reported To suppress the short channel effect, a novel self-aligned double-gate MOSFET, FinFET, is proposed By using boron-doped Si/sub 04/Ge/sub 06/ as a gate material, the desired threshold voltage was achieved for the ultrathin body device The quasiplanar nature of this new variant of the vertical double-gate MOSFETs can be fabricated relatively easily using the conventional planar MOSFET process technologies

FinFET-a self-aligned double-gate MOSFET scalable to 20 nm

This paper examines the effect of technology scaling and microarchitectural trends on the rate of soft errors in CMOS memory and logic circuits. We describe and validate an end-to-end model that enables us to compute the soft error rates (SER) for existing and future microprocessor-style designs. The model captures the effects of two important masking phenomena, electrical masking and latching-window masking, which inhibit soft errors in combinational logic. We quantify the SER due to high-energy neutrons in SRAM cells, latches, and logic circuits for feature sizes from 600 nm to 50 nm and clock periods from 16 to 6 fan-out-of-4 inverter delays. Our model predicts that the SER per chip of logic circuits will increase nine orders of magnitude from 1992 to 2011 and at that point will be comparable to the SER per chip of unprotected memory elements. Our result emphasizes that computer system designers must address the risks of soft errors in logic circuits for future designs.

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Modeling the effect of technology trends on the soft error rate of combinational logic

An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

This paper presents the current state of understanding of the factors that limit the continued scaling of Si complementary metal-oxide-semiconductor (CMOS) technology and provides an analysis of the ways in which application-related considerations enter into the determination of these limits. The physical origins of these limits are primarily in the tunneling currents, which leak through the various barriers in a MOS field-effect transistor (MOSFET) when it becomes very small, and in the thermally generated subthreshold currents. The dependence of these leakages on MOSFET geometry and structure is discussed along with design criteria for minimizing short-channel effects and other issues related to scaling. Scaling limits due to these leakage currents arise from application constraints related to power consumption and circuit functionality. We describe how these constraints work out for some of the most important application classes: dynamic random access memory (DRAM), static random access memory (SRAM), low-power portable devices, and moderate and high-performance CMOS logic. As a summary, we provide a table of our estimates of the scaling limits for various applications and device types. The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.

/pdf/device-scaling-limits-of-si-mosfets-and-their-application-299ftwsxth.pdf

Device scaling limits of Si MOSFETs and their application dependencies

The once-ephemeral radiation-induced soft error has become a key threat to advanced commercial electronic components and systems. Left unchallenged, soft errors have the potential for inducing the highest failure rate of all other reliability mechanisms combined. This article briefly reviews the types of failure modes for soft errors, the three dominant radiation mechanisms responsible for creating soft errors in terrestrial applications, and how these soft errors are generated by the collection of radiation-induced charge. The soft error sensitivity as a function of technology scaling for various memory and logic components is then presented with a consideration of which applications are most likely to require soft error mitigation.

/pdf/radiation-induced-soft-errors-in-advanced-semiconductor-1i5zuuxcs6.pdf

Radiation-induced soft errors in advanced semiconductor technologies

A scaling theory for double-gate SOI MOSFETs, which gives guidance for device design (silicon thickness t/sub si/; gate oxide thickness t/sub ox/) that maintains a subthreshold factor for a given gate length is discussed. According to the theory, a device can be designed with a gate length of less than 0.1 mu m while maintaining the ideal subthreshold factor. This is verified numerically with a two-dimensional device simulator. >

Scaling theory for double-gate SOI MOSFET's

Although it has been shown that cosmic ray neutrons play an important role in soft error (SE) phenomena, some important issues remain to be clarified in neutron-induced SE phenomena. This letter reports the geometric effect of multiple-bit SE's induced by neutrons. Multiple-bit SE's in 16 Mb DRAM's are investigated and their geometric effects on high reliability systems are discussed.

Geometric effect of multiple-bit soft errors induced by cosmic ray neutrons on DRAM's

Solving a two-dimensional (2-D) Poisson equation and assuming the minimum potential determines the threshold voltage, V/sub th/, we derived a model for V/sub th/ of short channel double-gate SOI MOSFETs, and verified its validity by comparing with numerical data. We evaluated the threshold voltage lowering, /spl Delta/V/sub th/, and subthreshold swing (S-swing) degradation with decreasing gate length L/sub G/, and showed that we can design a 0.05-/spl mu/m-L/sub G/ device with /spl Delta/V/sub th/ of less than 50 mV and an S-swing of less than 70 mV/decade if 10-nm-thick SOI is available.

Analytical threshold voltage model for short channel double-gate SOI MOSFETs

The authors review two types of simulators for the analysis of cosmic ray neutron-induced soft errors (SEs). One of them is the neutron-induced soft error simulator (NISES). A recently proposed nuclear reaction theory forms the foundation for the nuclear reaction database used in NISES. The other simulator, the simplified simulator MBGR, is based on a modified version of the burst generation rate (BGR) model. Both simulators accurately simulate neutron-induced SE rates (SERs). MBGR actually provides an easier and quicker estimation of neutron-induced SER's than NISES. On the other hand, NISES covers more applications: it simulates neutron-induced charge collection, multiple-bit SE, and /spl alpha/-induced SE analysis.

Simulation technologies for cosmic ray neutron-induced soft errors: Models and simulation systems

Neutron-induced soft error rates (SERs) of subhalf-micron CMOS SRAM and Latch circuits were studied both experimentally and analytically to investigate cosmic ray neutron-induced soft errors (SEs). Because the neutron beam used in the measurement has an energy spectrum similar to that of sea-level atmospheric neutrons, our SER data corresponds to those induced by cosmic ray neutrons. The /spl alpha/-particle induced SERs were also measured for comparison with the neutron-induced SER's. Neutron-induced SEs occurred in both circuits. On the other hand, /spl alpha/-induced SEs occurred in SRAM, but not in the Latch circuits. The measured SERs agreed with simulated results. We discussed the significance of how cosmic ray neutrons affects CMOS circuits at ground level.

Yoshiharu Tosaka

Papers

Scaling theory for double-gate SOI MOSFET's

Geometric effect of multiple-bit soft errors induced by cosmic ray neutrons on DRAM's

Analytical threshold voltage model for short channel double-gate SOI MOSFETs

Simulation technologies for cosmic ray neutron-induced soft errors: Models and simulation systems

Measurement and analysis of neutron-induced soft errors in sub-half-micron CMOS circuits