Yoshihiro Hayashi

Bio: Yoshihiro Hayashi is an academic researcher from NEC. The author has contributed to research in topics: Copper interconnect & Polishing. The author has an hindex of 26, co-authored 198 publications receiving 2664 citations.

Method of stacking semiconductor substrates for fabrication of three-dimensional integrated circuit

Abstract: A semiconductor substrate stacking method comprises the steps of preparing first and second thin film devices each in the form of a thin film having a connection electrode formed on an upper surface thereof and a connection electrode formed on an undersurface thereof, each of the thin film devices being bonded at its upper surface thereof to a support plate by adhesive. The first thin film device is stacked and bonded onto a base substrate having a device formed thereon and a connection electrode formed on the device, in such a manner that the device formed on the base substrate faces the undersurface of the first thin film device and the connection electrode formed on the device formed on the base substrate is in alignment with and in contact with the undersurface connection electrode formed on the first thin film device. The support plate and the adhesive of the first thin film device are removed so that the upper surface of the first thin film device and the upper surface connection electrode formed on the upper surface of the first thin film device are exposed. Similarly, the second thin film device is stacked and bonded onto the first thin film device stacked on the base substrate and the support plate and the adhesive of the second thin film device is removed.

Three dimensional ICs, having four stacked active device layers

Abstract: The four-layer-stacked master slice is proposed as a system application for 3-D ICs. The master slice consists of a programmable logic array for logic circuits, a CMOS gate array for I/O interface buffer circuits, and a CMOS SRAM. Fabrication technologies for the four-layer-stacked 3-D IC are described. Laser beam recrystallization was carried out for the formation of three SOI (silicon-on-insulator) layers in the 3-D IC. Recrystallization without cracks in both SOI and vertical isolation layers was accomplished by adjusting laser annealing conditions. Microprobe Raman spectroscopy data indicated that a tensile stress of (3-6)*10/sup 9/ dyne/cm/sup 2/ was present in each SOI layer. Surface planarization of the vertical isolation layer was carried out with a combination of polystyrene spin coating and dry etching. An initial surface roughness of about 1.7 mu m was successfully reduced to less than 500 A, and the planarized surface did not interfere with either recrystallization or photolithography. NMOSFETs and PMOSFETs, fabricated in the four-layer-stacked 3-D IC, have been successfully operated. >

New analysis methods for comprehensive understanding of Random Telegraph Noise

Abstract: New analysis methods useful for understanding both complex waveforms and statistical behaviors of Random Telegraph Noise (RTN) are proposed. Complex waveforms are clearly visualized using Time Lag Plots. Bias dependence of statistically extracted average trap number is discussed, with emphasis on the importance of undetectable traps on product reliability.

Fabrication of three-dimensional IC using `cumulatively bonded IC' (CUBIC) technology

Abstract: A technology is proposed for the fabrication of three-dimensional integrated circuits (3D-ICs) having a large number of device layers, referred to as `cumulatively bonded IC' (CUBIC) technology wherein several thin-film devices are bonded cumulatively. The technology was used to fabricate a two-active-layer device having a bulk-Si NMOSFET lower layer and a thinned NMOSFET upper layer. The CUBIC technology, essentially a face-to-back device bonding technology, is applicable to fabricating 3D-ICs having more than three active-device layers. The process consists of two subprocesses-wafer thinning and thin-film lamination. Preferential polishing was used for wafer thinning and bump/tool contacts were used for device-to-device vertical interconnections

Single-charge-based modeling of transistor characteristics fluctuations based on statistical measurement of RTN amplitude

Abstract: A single-charge-based random fluctuation model suited for analyzing both random telegraph noise (RTN) and intrinsic channel transistors (UTB-SOI, FinFET etc) is proposed Combining a quantitative formula for the worst case V TH shift (ΔV TH ) with measured data of RTN amplitude distributions, it is shown that RTN should not be ignored for scaled SRAM design The model also shows that scaling of intrinsic channel FETs will be limited by the fluctuations caused by residual random charge, which rapidly increase in proportion to 1/LW

Semiconductor device, and manufacturing method thereof

Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication

Abstract: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Three dimensional structure memory

Abstract: A Three Dimensional Structure (3DS) Memory (100) allows for physical separation of the memory circuits (103) and the control logic circuit (101) onto different layers (103) such that each layer may be separately optimized. One control logic circuit (101) suffices for several memory circuits (103), reducing cost. Fabrication of 3DS memory (100) involves thinning of the memory circuit (103) to less than 50 microns in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections (105) are used. The 3DS memory (100) manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration

Abstract: Performance of deep-submicrometer very large scale integrated (VLSI) circuits is being increasingly dominated by the interconnects due to decreasing wire pitch and increasing die size. Additionally, heterogeneous integration of different technologies in one single chip is becoming increasingly desirable, for which planar (two-dimensional) ICs may not be suitable. This paper analyzes the limitations of the existing interconnect technologies and design methodologies and presents a novel three-dimensional (3-D) chip design strategy that exploits the vertical dimension to alleviate the interconnect related problems and to facilitate heterogeneous integration of technologies to realize a system-on-a-chip (SoC) design. A comprehensive analytical treatment of these 3-D ICs has been presented and it has been shown that by simply dividing a planar chip into separate blocks, each occurring a separate physical level interconnected by short and vertical interlayer interconnects (VILICs), significant improvement in performance and reduction in wire-limited chip area can be achieved, without the aid of any other circuit or design innovations. A scheme to optimize the interconnect distribution among different interconnect tiers is presented and the effect of transferring the repeaters to upper Si layers has been quantified in this analysis for a two-layer 3-D chip. Furthermore, one of the major concerns in 3-D ICs arising due to power dissipation problems has been analyzed and an analytical model has been presented to estimate the temperatures of the different active layers. It is demonstrated that advancement in heat sinking technology will be necessary in order to extract maximum performance from these chips. Implications of 3-D device architecture on several design issues have also been discussed with special attention to SoC design strategies. Finally some of the promising technologies for manufacturing 3-D ICs have been outlined.

Three-dimensional integrated circuits

Abstract: Three-dimensional (3D) integrated circuits (ICs), which contain multiple layers of active devices, have the potential to dramatically enhance chip performance, functionality, and device packing density. They also provide for microchip architecture and may facilitate the integration of heterogeneous materials, devices, and signals. However, before these advantages can be realized, key technology challenges of 3D ICs must be addressed. More specifically, the processes required to build circuits with multiple layers of active devices must be compatible with current state-of-the-art silicon processing technology. These processes must also show manufacturability, i.e., reliability, good yield, maturity, and reasonable cost. To meet these requirements, IBM has introduced a scheme for building 3D ICs based on the layer transfer of functional circuits, and many process and design innovations have been implemented. This paper reviews the process steps and design aspects that were developed at IBM to enable the formation of stacked device layers. Details regarding an optimized layer transfer process are presented, including the descriptions of 1) a glass substrate process to enable through-wafer alignment; 2) oxide fusion bonding and wafer bow compensation methods for improved alignment tolerance during bonding; 3) and a single-damascene patterning and metallization method for the creation of high-aspect-ratio (6:1 108 vias/cm2), and extremely aggressive wafer-to-wafer alignment (submicron) capability.