Young-Bog Park

Bio: Young-Bog Park is an academic researcher from Motorola. The author has contributed to research in topics: Flicker noise & Time-dependent gate oxide breakdown. The author has an hindex of 2, co-authored 2 publications receiving 149 citations.

Degradation of thin tunnel gate oxide under constant Fowler-Nordheim current stress for a flash EEPROM

Abstract: The degradation of thin tunnel gate oxide under constant Fowler-Nordheim (FN) current stress was studied using flash EEPROM structures. The degradation is a strong function of the amount of injected charge density (Q/sub inj/), oxide thickness, and the direction of stress. Positive charge trapping is usually dominant at low Q/sub inj/ followed by negative charge trapping at high Q/sub inj/, causing a turnaround of gate voltage and threshold voltage. Interface trap generation continues to increase with increasing stress, as evidenced by subthreshold slope and transconductance. Gate injection stress creates more positive charge traps and interface traps than does substrate injection stress. Oxide degradation gets more severe for thicker oxide, due to more oxide charge trapping and interface trap generation by impact ionization. A simple model of oxide degradation and breakdown was established based on the experimental results. It indicates that the damage in the oxide is more serious near the anode interface by impact ionization and oxide breakdown is also closely related to surface roughness at the cathode interface. When all the damage sites in the oxide connect and a conductive path between cathode and anode is formed, oxide breakdown occurs. The damage is more serious for thicker oxide because a thicker oxide is more susceptible to impact ionization.

High frequency noise characteristics of RF MOSFETs in subthreshold region

Abstract: High frequency noise characteristics of 0.13um and 0.18um n-type MOSFET across a full range of bias conditions is presented in this paper. Focus is mainly on nMOSFET's behavior in "off" state, which is not predicted accurately by existing commercial models. This is a region especially important for full-chip RFCMOS design. In this paper, noise parameters (NFmin, RN, /spl Gamma/opt) up to 6GHz are investigated in detail. From the device perspective, the power spectral density of channel noise and induced gate noise is also studied to understand how MOSFETs actually operate from strong inversion to weak inversion and depletion.

Modified derivative superposition method for linearizing FET low noise amplifiers

Abstract: Intermodulation distortion in field-effect transistors (FETs) at RF frequencies is analyzed using the Volterra-series analysis. The degrading effect of the circuit reactances on the maximum IIP3 in the conventional derivative-superposition (DS) method is explained. The noise performance of this method is also analyzed and the effect of the subthreshold biasing of one of the FETs on the noise figure (NF) is shown. A modified DS method is proposed to increase the maximum IIP3 at RF. It was used in a 0.25-mum Si CMOS low-noise amplifier (LNA) designed for cellular code-division multiple-access receivers. The LNA achieved +22-dBm IIP3 with 15.5-dB gain, 1.65-dB NF, and 9.3 mA@2.6-V power consumption

Device and technology evolution for Si-based RF integrated circuits

Abstract: The relationships between device feature size and device performance figures of merit (FoMs) are more complex for radio frequency (RF) applications than for digital applications. Using the devices in the key circuit blocks for typical RF transceivers, we review and give trends for the FoMs that characterize active and passive RF devices. These FoMs include transit frequency at unity current gain f/sub T/, maximum frequency of oscillation f/sub MAX/ at unit power gain, noise, breakdown voltage, capacitor density, varactor and inductor quality, and the like. We use the specifications for wireless communications systems to show how different Si-based devices may achieve acceptable FoMs. We focus on Si complementary metal-oxide-semiconductor (CMOS), Si Bipolar CMOS, and Si bipolar devices, including SiGe heterojunction bipolar transistors, RF devices, and integrated circuits (ICs). We analyze trends in the FoMs for Si-based RF devices and ICs and show how these trends relate to the technology nodes of the 2003 International Technology Roadmap for Semiconductors. We also compare FoMs for the best reported performance of research devices and for the performance of devices manufactured in high volumes, typically more than 10 000 devices. Certain commercial equipment, instruments, or materials are identified in this article to specify adequately the experimental or theoretical procedures. Such identification does not imply recommendation by any of the host institutions of the authors, nor does it imply that the equipment or materials are necessarily the best available for the intended purpose.

Effects of interface trap generation and annihilation on the data retention characteristics of flash memory cells

Abstract: It is revealed that the interface trap generation rate increases by Fowler-Nordheim current stressing on the tunnel oxide as the channel width of shallow-trench isolation (STI)-isolated NAND flash cells shrinks. Furthermore, we argue that the interface trap annihilation phenomenon during retention mode becomes a major failure mechanism of the data retention characteristics of sub-100-nm cells in addition to the conventional charge loss mechanism. A new interface trap analysis method using the hysteresis of the I/sub d/--V/sub g/ curve is proposed and shows that the interface traps consist of fast traps and slow traps.

A 0.4-V Low Noise Amplifier Using Forward Body Bias Technology for 5 GHz Application

Abstract: A fully integrated low noise amplifier (LNA) suitable for ultra low voltage and ultra low power applications is proposed and demonstrated in 0.13 mum CMOS technology. In order to meet the requirement of ultra low voltage applications, a two-stage common-source configuration is employed. By using forward-body-biased metal oxide semiconductor field effect transistors, the proposed LNA can operate at 0.4 V supply voltage, successfully demonstrating the application potential of dynamic threshold voltage technology in the radio frequency region. The experimental results show that the proposed LNA has a 10.3 dB power gain and a 5.3 dB noise figure, while consuming only 1.03 mW dc power with an ultra low supply voltage of 0.4 V.

A Low-Power Fully Monolithic Subthreshold CMOS Receiver With Integrated LO Generation for 2.4 GHz Wireless PAN Applications

Abstract: This paper reports a fully monolithic subthreshold CMOS receiver with integrated subthreshold quadrature LO chain for 2.4 GHz WPAN applications. Subthreshold operation, passive voltage boosting, and various low-power circuit techniques such as current reuse, stacking, and differential cross coupling have been combined to lower the total power consumption. The subthreshold receiver, consisting of the switched-gain low noise amplifier, the quadrature mixers, and the variable gain amplifiers, consumes only 1.4 mW of power and has a gain of 43 dB and a noise figure of 5 dB. The entire quadrature LO chain, including a stacked quadrature VCO and differential cross-coupled buffers, also operates in the subthreshold region and consumes a total power of 1.2 mW. The subthreshold receiver with integrated LO generation is implemented in a 0.18 mum CMOS process. The receiver has a 3-dB IF bandwidth of 95 MHz.