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Author

Young H. Kwark

Other affiliations: National Security Agency
Bio: Young H. Kwark is an academic researcher from IBM. The author has contributed to research in topics: Printed circuit board & Multi-mode optical fiber. The author has an hindex of 28, co-authored 123 publications receiving 3133 citations. Previous affiliations of Young H. Kwark include National Security Agency.


Papers
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Journal ArticleDOI
TL;DR: In this paper, a chip-like optoelectronic packaging structure (Optochip), assembled directly onto an organic card (Optocard), is developed for supporting terabit/second chip-to-chip data transfers over organic cards within high-performance servers, switch routers, and other intensive computing systems.
Abstract: In the "Terabus" optical interconnect program, optical data bus technologies are developed that will support terabit/second chip-to-chip data transfers over organic cards within high-performance servers, switch routers, and other intensive computing systems. A complete technology set is developed for this purpose, based on a chip-like optoelectronic packaging structure (Optochip), assembled directly onto an organic card (Optocard). Vertical-cavity surface emitting laser (VCSEL) and photodiode arrays (4times12) are flip-chip bonded to the driver and receiver IC arrays implemented in 0.13-mum CMOS. The IC arrays are in turn flip-chip assembled onto a 1.2-cm2 silicon carrier interposer to complete the transmitter and receiver Optochips. The organic Optocard incorporates 48 parallel multimode optical waveguides on a 62.5-mum pitch. A simple scheme for optical coupling between the Optochip and the Optocard is developed, based on a single-lens array etched onto the backside of the optoelectronic arrays and on 45deg mirrors in the waveguides. Transmitter and receiver operation is demonstrated up to 20 and 14 Gb/s per channel, respectively. The power dissipation of 10-Gb/s single-channel links over multimode fiber is as low as 50 mW

262 citations

Journal ArticleDOI
TL;DR: The technical challenges and recent progress made in the development of silicon carrier technology for potential new applications are described.
Abstract: System-on-Package (SOP) technology based on silicon carriers has the potential to provide modular design flexibility and high-performance integration of heterogeneous chip technologies and to support robust chip manufacturing with high-yield/low-cost chips for a wide range of two- and three-dimensional product applications. Key technology enablers include silicon through-vias, high-density wiring, high-I/O chip interconnection, and supporting test and assembly technologies. The silicon through-vias are a key feature permitting efficient area array signal, power, and ground interconnection through these thinned silicon packages. High-density wiring and high-density chip I/O interconnection can enable tight integration of heterogeneous chip technologies which approximate the performance of an integrated system-on-chip with a "virtual chip" using the silicon package for integration. Silicon carrier fabrication leverages existing manufacturing capability and mid-UV lithography to provide very dense package wiring following CMOS back-end-of-line design rules. Further, the thermal expansion of the silicon carrier package matches the chip, which helps maintain reliability even as the high-density chip microbump interconnections scale to smaller size. In addition to heterogeneous chip integration, SOP products may leverage the integration of passive components, active devices, and electro-optic structures to enhance system-level performance while also maintaining functional test capability and known good chips when needed. This paper describes the technical challenges and recent progress made in the development of silicon carrier technology for potential new applications.

246 citations

Journal ArticleDOI
TL;DR: In this paper, a 90-nm CMOS 10-Gb/s transceiver for chip-to-chip communications is presented, where a 5-tap decision feedback equalizer is included in the receiver and a 4-tap baud-spaced feed-forward equalizer (FFE) in the transmitter.
Abstract: This paper presents a 90-nm CMOS 10-Gb/s transceiver for chip-to-chip communications. To mitigate the effects of channel loss and other impairments, a 5-tap decision feedback equalizer (DFE) is included in the receiver and a 4-tap baud-spaced feed-forward equalizer (FFE) in the transmitter. This combination of DFE and FFE permits error-free NRZ signaling over channels with losses exceeding 30 dB. Low jitter clocks for the transmitter and receiver are supplied by a PLL with LC VCO. Operation at 10-Gb/s with good power efficiency is achieved by using half-rate architectures in both transmitter and receiver. With the transmitter producing an output signal of 1200mVppd, one transmitter/receiver pair and one PLL consume 300mW. Design enhancements of a half-rate DFE employing one tap of speculative feedback and four taps of dynamic feedback allow its loop timing requirements to be met. Serial link experiments with a variety of test channels demonstrate the effectiveness of the FFE/DFE equalization

237 citations

Journal ArticleDOI
TL;DR: In this article, the authors show that inductors with high Q's for lumped-element designs in the 1-10 GHz range and transmission lines with low losses for distributed element designs beyond 10 GHz can be made available with the proposed adjustments to commercial silicon technology.
Abstract: Spiral inductors and different types of transmission lines are fabricated by using copper (Cu)-damascene interconnects and high-resistivity silicon (HRS) or sapphire substrates. The fabrication process is compatible with the concepts of silicon device fabrication. Spiral inductors with 1.4-nH inductance have quality factors (Q) of 30 at 5.2 GHz and 40 at 5.8 GHz for the HRS and the sapphire substrates, respectively. 80-nH inductors have Q's as high as 13. The transmission-line losses are near 4 dB/cm at 10 GHz for microstrips, inverted microstrips, and coplanar lines, which are sufficiently small for maximum line lengths within typical silicon-chip areas. This paper shows that inductors with high Q's for lumped-element designs in the 1-10-GHz range and transmission lines with low losses for distributed-element designs beyond 10 GHz can be made available with the proposed adjustments to commercial silicon technology.

172 citations

Journal ArticleDOI
TL;DR: In this paper, an analytical model for vias and traces is presented for simulation of multilayer interconnects at the package and printed circuit board levels, which can be applied to efficiently simulate a wide range of structures.
Abstract: Analytical models for vias and traces are presented for simulation of multilayer interconnects at the package and printed circuit board levels. Vias are modeled using an analytical formulation for the parallel-plate impedance and capacitive elements, whereas the trace-via transitions are described by modal decomposition. It is shown that the models can be applied to efficiently simulate a wide range of structures. Different scenarios are analyzed including thru-hole and buried vias, power vias, and coupled traces routed into different layers. By virtue of the modal decomposition, the proposed method is general enough to handle structures with mixed reference planes. For the first time, these models have been validated against full-wave methods and measurements up to 40 GHz. An improvement on the computation speed of at least two orders of magnitude has been observed with respect to full-wave simulations.

153 citations


Cited by
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Journal ArticleDOI
10 Jun 2009
TL;DR: The current performance and future demands of interconnects to and on silicon chips are examined and the requirements for optoelectronic and optical devices are project if optics is to solve the major problems of interConnects for future high-performance silicon chips.
Abstract: We examine the current performance and future demands of interconnects to and on silicon chips. We compare electrical and optical interconnects and project the requirements for optoelectronic and optical devices if optics is to solve the major problems of interconnects for future high-performance silicon chips. Optics has potential benefits in interconnect density, energy, and timing. The necessity of low interconnect energy imposes low limits especially on the energy of the optical output devices, with a ~ 10 fJ/bit device energy target emerging. Some optical modulators and radical laser approaches may meet this requirement. Low (e.g., a few femtofarads or less) photodetector capacitance is important. Very compact wavelength splitters are essential for connecting the information to fibers. Dense waveguides are necessary on-chip or on boards for guided wave optical approaches, especially if very high clock rates or dense wavelength-division multiplexing (WDM) is to be avoided. Free-space optics potentially can handle the necessary bandwidths even without fast clocks or WDM. With such technology, however, optics may enable the continued scaling of interconnect capacity required by future chips.

1,959 citations

Patent
01 Aug 2008
TL;DR: In this article, the oxide semiconductor film has at least a crystallized region in a channel region, which is defined as a region of interest (ROI) for a semiconductor device.
Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

1,501 citations

Journal ArticleDOI
TL;DR: In this article, the authors provide an overview and outlook for the silicon waveguide platform, optical sources, optical modulators, photodetectors, integration approaches, packaging, applications of silicon photonics and approaches required to satisfy applications at mid-infrared wavelengths.
Abstract: Silicon photonics research can be dated back to the 1980s. However, the previous decade has witnessed an explosive growth in the field. Silicon photonics is a disruptive technology that is poised to revolutionize a number of application areas, for example, data centers, high-performance computing and sensing. The key driving force behind silicon photonics is the ability to use CMOS-like fabrication resulting in high-volume production at low cost. This is a key enabling factor for bringing photonics to a range of technology areas where the costs of implementation using traditional photonic elements such as those used for the telecommunications industry would be prohibitive. Silicon does however have a number of shortcomings as a photonic material. In its basic form it is not an ideal material in which to produce light sources, optical modulators or photodetectors for example. A wealth of research effort from both academia and industry in recent years has fueled the demonstration of multiple solutions to these and other problems, and as time progresses new approaches are increasingly being conceived. It is clear that silicon photonics has a bright future. However, with a growing number of approaches available, what will the silicon photonic integrated circuit of the future look like? This roadmap on silicon photonics delves into the different technology and application areas of the field giving an insight into the state-of-the-art as well as current and future challenges faced by researchers worldwide. Contributions authored by experts from both industry and academia provide an overview and outlook for the silicon waveguide platform, optical sources, optical modulators, photodetectors, integration approaches, packaging, applications of silicon photonics and approaches required to satisfy applications at mid-infrared wavelengths. Advances in science and technology required to meet challenges faced by the field in each of these areas are also addressed together with predictions of where the field is destined to reach.

939 citations