Youngoo Yang

TL;DR: In this paper, a fully matched N-way Doherty amplifier with two-, three-, and four-way structures is presented. And the linearity performance of the Doherty amplifiers is optimized for better efficiency versus linearity by a bias adjustment of the peaking amplifiers.

TL;DR: In this paper, the authors presented analytic and experimental comparisons for high-efficiency class-F and inverse-class-F amplifiers, where the analytic formula of the efficiencies, output powers, dc power dissipations and fundamental load impedances of both amplifiers were derived from the ideal current and voltage waveforms.

TL;DR: In this article, a Doherty amplifier with full load matching circuits of the carrier and peaking amplifiers at both low and high power levels is demonstrated for the first time, and the circuit elements and bias points are designed and optimized using a large-signal harmonic balance simulation to offer simultaneous improvements in linearity and efficiency.

TL;DR: In this article, a 2.14 GHz Doherty amplifier is implemented using 4-W PEP LDMOSFETs, and an adaptive controlled gate bias circuit is constructed and the control shape is optimized experimentally.

TL;DR: In this article, a 2.45 GHz fully differential CMOS power amplifier with high efficiency and linearity is presented, where an optimum gate bias is applied for the cancellation of the nonlinear harmonic generated by g/sub m3/ and a new harmonic termination technique at the common source node along with normal harmonic termination at the drain.