Yu Bi

Bio: Yu Bi is an academic researcher from Delft University of Technology. The author has contributed to research in topics: Sensitivity (control systems) & Capacitance. The author has an hindex of 6, co-authored 8 publications receiving 315 citations.

A 26 $\mu$ W 8 bit 10 MS/s Asynchronous SAR ADC for Low Energy Radios

Abstract: This paper presents an asynchronous SAR ADC for flexible, low energy radios. To achieve excellent power efficiency for a relatively moderate resolution, various techniques are introduced to reduce the power consumption: custom-designed 0.5 fF unit capacitors minimize the analog power consumption while asynchronous dynamic logic minimizes the digital power consumption. The variability of the custom-designed capacitors is estimated by a specialized CAD tool and verified by chip measurements. An implemented 8-bit prototype in a 90 nm CMOS technology occupies 228 μm × 240 μm including decoupling capacitors, and achieves an ENOB of 7.77 bit at a sampling frequency of 10.24 MS/s. The power consumption equals 26.3 μW from a 1 V supply, thus resulting in an energy efficiency of 12 fJ/conversion-step. Moreover, the fully dynamic design, which is optimized for low-leakage, leads to a standby power consumption of 6 nW. In that way, the energy efficiency of this converter can be maintained down to very low sampling rates.

Sensitivity computation of interconnect capacitances with respect to geometric parameters

Abstract: This paper presents an algorithm that enables an extension of standard 3d capacitance extraction to take into account the effects of small dimensional variations of interconnects by calculating the corresponding capacitance sensitivities. By using an adjoint technique, capacitances and their sensitivities w.r.t. multiple geometric parameters can be obtained with one-time 3d extraction using the boundary element method (BEM).

Efficient sensitivity-based capacitance modeling for systematic and random geometric variations

Abstract: This paper presents a highly efficient sensitivity-based method for capacitance extraction, which models both systematic and random geometric variations. This method is applicable for BEM-based Layout Parasitic Extraction (LPE) tools. It is shown that, with only one system solve, the nominal parasitic capacitances as well as its relative standard deviations caused by both systematic and random geometric variations can be obtained. The additional calculation for both variations can be done at a very modest computational time, which is negligible compared to that of the standard capacitance extraction without considering any variation. Specifically, using the proposed method, experiments and a case study have been analyzed to show the impact of the random variation on the capacitance for a real design.

Sensitivity computation using domain-decomposition for boundary element method based capacitance extractors

Abstract: The on-going reduction of the on-chip feature size goes together with an increase of process variability. While the manufacturer is expected to improve the uniformity of its output, and the designers are expected to enhance circuit adaptability and reliability, the design tools are expected to deliver convenient and fast approaches capable of giving accurate characterizations of manufacturing tolerances. In this paper, we present an algorithm that enables an extension of 3-D capacitance extractors to generate both the nominal capacitances and their sensitivities w.r.t. all geometric parameters with only one extraction. Using the domain-decomposition technique, it is shown that sensitivities can be derived from the intermediate data of the standard capacitance extraction using the Boundary Element Method (BEM). The algorithm has been implemented in a layout-to-circuit extractor. It is shown by experiments that the additional cost for the sensitivity computation is less than 20% of the standard time consumption, essentially independent of the number of parameters.

Capacitance Sensitivity Calculation for Interconnects by Adjoint Field Technique

Abstract: This paper presents a new, efficient algorithm for capacitance sensitivity calculation w.r.t. geometric variations due to process imperfection of interconnects. Sensitivity calculation can be a very important step in variation-aware interconnect analysis. The algorithm is based on the adjoint field technique (AFT) derived from an application of Tellegen's theorem for the electrostatic (ES) field. The algorithm relies on manipulating the intermediate data of a standard (without considering variations) capacitance extraction. Thus no additional costly computations are required, which makes the algorithm very efficient. The algorithm has been verified for 2D structures while the generalization for 3D structures is straightforward.

22.4 A 1GS/s 10b 18.9mW time-interleaved SAR ADC with background timing-skew calibration

Abstract: SARs are one of the most energy-efficient ADC architectures for medium resolution and low-to-medium speed. To improve the limited bandwidth of SAR ADCs, the time-interleaved (TI) structure is often used [1,2]. However, TI ADCs have several issues caused by mismatches between channels, such as offset, gain, and timing-skew errors. Unlike the other errors, timing-skew causes errors that increase with input signal frequency. Considering that the TI structure is typically employed to increase bandwidth, timing-skew can be a dominant error source of TI ADCs. Recent works [1,3] have demonstrated a background timing-skew calibration using a dedicated additional channel as a timing reference. In this work, we present a TI SAR ADC that enables background timing-skew calibration without a separate timing reference channel and enhances the conversion speed of each channel.

A 10b/12b 40 kS/s SAR ADC With Data-Driven Noise Reduction Achieving up to 10.1b ENOB at 2.2 fJ/Conversion-Step

Abstract: This paper presents a power-efficient 10/12 bit 40 kS/s SAR ADC for sensor applications. It supports resolutions of 10 and 12 bit and sample rates from DC up to 40 kS/s to accommodate a variety of sensor applications. A Data-Driven Noise-Reduction method is introduced to selectively enhance the comparator noise performance. In this way, a higher ADC resolution can be achieved with a small increase of the power consumption. A self-oscillating comparator is used to generate the bit-cycling clock internally. In this way, the ADC only requires an external clock at the sample-rate frequency. A segmented capacitive DAC with 250 aF unit elements is applied to save power and to reduce DNL errors at the same time. The implemented prototype in 65 nm CMOS occupies an area of 0.076 mm 2. For the two supported resolutions (10/12 bit), the ADC achieves an ENOB of 9.4 and 10.1 bit while consuming 72 and 97 nW from a 0.6 V supply at 40 kS/s. This leads to power efficiencies of 2.7 and 2.2 fJ/conversion-step for 10 bit and 12 bit resolution, respectively. Furthermore, the leakage power, which is below 0.4 nW, ensures that the efficiency can be maintained down to very low sample rates.

A 1.9nJ/b 2.4GHz multistandard (Bluetooth Low Energy/Zigbee/IEEE802.15.6) transceiver for personal/body-area networks

Abstract: This paper presents a multistandard ultra-low-power (ULP) 2.36/2.4GHz transceiver for personal and body-area networks (PAN/BAN). The presented radio complies with 3 short-range standards: Bluetooth Low Energy (BT-LE), IEEE802.15.4 (ZigBee) and IEEE802.15.6 (Medical Body-Area Networks, MBAN). A proprietary 2Mb/s mode is also implemented to support data-streaming applications like hearing aids. Current short-range radios for Zigbee and BT-LE typically consume more than 20mW DC power, which is rather high for autonomous systems with limited battery energy. The dual-mode MBAN/BT-LE transceiver achieves a power consumption of 6.5mW for the RX and 5.9mW for the TX by employing a sliding-IF RX and a polar TX architecture. However, it suffers from limited RX image rejection and needs a PA operating at a higher supply voltage. In this paper, an energy-efficient radio architecture with a suitable LO frequency plan is selected, and several efficiency-enhancement techniques for the critical RF circuits (e.g., a push-pull mixer and a digitally-assisted PA) are utilized. As a result, the presented transceiver dissipates only 3.8mW (RX) and 4.6mW (TX) DC power from a 1.2V supply, while exceeding all of the PHY requirements of above 3 standards.

An Injectable 64 nW ECG Mixed-Signal SoC in 65 nm for Arrhythmia Monitoring

Abstract: A syringe-implantable electrocardiography (ECG) monitoring system is proposed. The noise optimization and circuit techniques in the analog front-end (AFE) enable 31 nA current consumption while a minimum energy computation approach in the digital back-end reduces digital energy consumption by 40%. The proposed SoC is fabricated in 65 nm CMOS and consumes 64 nW while successfully detecting atrial fibrillation arrhythmia and storing the irregular waveform in memory in experiments using an ECG simulator, a live sheep, and an isolated sheep heart.

Energy-Efficient Cooperative Spectrum Sensing: A Survey

Abstract: The article analyzes the problem of energy efficient techniques in cooperative spectrum sensing (CSS). Although it was proven that single-device sensing is not sufficient for reliable sensing, cooperative spectrum sensing was proposed, burdened, however, with great overhead. Thus, work on the topic of energy efficient cooperative schemes gained more interest, which resulted in a number of energy efficient cooperative algorithm proposals. In this work, we try to classify the possible directions in energy efficient CSS and present a limited set of works introducing new ideas to an energy efficient CSS algorithm.