This paper presents a one-transistor dynamic random access memory (1T-DRAM) based on a novel surrounding-gate transistor with wide trenched body (WT-SGT). This 1T-DRAM exhibits favorable transient performance after word line (WL)/bit line (BL) disturbance, which is verified using Sentaurus TCAD 12.0. The proposed memory cell can be fabricated with a feature area of 4 $\mathrm{F}^{2 }$ and with processes that are fully compatible with conventional CMOS technology. Extended simulations reveal three key findings. First, the WT-SGT achieves a high-speed programming operation (1.17 ns) at a low operating voltage (1.6 V) and with a programming window that can be further extended by widening its trenched body. Second, the recombination rate is also reduced, thereby yielding an acceptable retention time (RT) of 625.6 ms. Third, the decreased RT after a 100-ns WL/BL disturbance is improved by 33%, as compared with a conventional SGT 1T-DRAM. We, therefore, believe that this new device will become a competitive candidate for use in future DRAM cells.

Transient and Thermal Analysis on Disturbance Immunity for 4 $\mathrm{F}^{2}$ Surrounding Gate 1T-DRAM With Wide Trenched Body

Recent advances in semiconductor technology provide us with the resources to explore alternative methods for fabricating transistors with the goal of further reducing their sizes to increase transistor density and enhance performance. Conventional transistors use semiconductor junctions; they are formed by doping atoms on the silicon substrate that makes p-type and n-type regions. Decreasing the size of such transistors means that the junctions will get closer, which becomes very challenging when the size is reduced to the lower end of the nanometer scale due to the requirement of extremely high gradients in doping concentration. One of the most promising solutions to overcome this issue is realizing junctionless transistors. The first junctionless device was fabricated in 2010 and, since then, many other transistors of this kind (such as FinFET, Gate-All-Around, Thin Film) have been proposed and investigated. All of these semiconductor devices are characterized by junctionless structures, but they differ from each other when considering the influence of technological parameters on their performance. The aim of this review paper is to provide a simple but complete analysis of junctionless transistors, which have been proposed in the last decade. In this work, junctionless transistors are classified based on their geometrical structures, analytical model, and electrical characteristics. Finally, we used figure of merits, such as I o n / I o f f , D I B L , and S S , to highlight the advantages and disadvantages of each junctionless transistor category.

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Junctionless Transistors: State-of-the-Art

A vertical silicon-on-insulator (VSOI)-based capacitorless 1T-DRAM cell with a trench body structure is proposed. The trench body is added as an additional neutral region under the device channel region through a self-aligned fabrication process in a 300 nm wide VSOI MOSFET that enables the device to separate the hole storage region and sense electron current region without extra area penalty. With the holes stored in the trench body, the floating-body effect occurs and affects the threshold voltage significantly. A Synopsys TCAD software tool is also used to evaluate the device performance for DC and transient analysis. The electrical and transient characteristics confirm how the proposed device with trench body can be used perfectly as a 1T-DRAM application to achieve desirable performance in terms of a larger programming window and longer retention time.

Novel Vertical SOI-Based 1T-DRAM With Trench Body Structure

Based on the device and equivalent transistor model, we present a short-channel-effect (SCE)-degraded noise margin (NM) model for junctionless double-gate MOSFET working on subthreshold CMOS logic gate. The device parameters such as the thick silicon thickness, thick gate oxide thickness, high doping density, and short channel length can severely degrade the NM due to serious SCE. By contrast, both the small subthreshold slope $\eta $ and the balanced transistor strength S can suppress the NM degradation more efficiently. The required minimum supply voltage $V_{\mathrm {\mathbf {dd,min}}}$ for the subthreshold CMOS logic gate is derived by the criterion of the NM larger than thermal noise to ensure the correct logic gate operation. Being similar to drain-induced barrier lowering, allowable NM corresponding to the minimum channel length can also be uniquely controlled and determined by the scaling factor according to the scaling theory.

A Short-Channel-Effect-Degraded Noise Margin Model for Junctionless Double-Gate MOSFET Working on Subthreshold CMOS Logic Gates

Based on the subthreshold current and equivalent transistor models, a new device-parameter-oriented average DC power model average DC power (PDC) for symmetric operation of junctionless double-gate mosfet (JLDGFET) working on the low-power CMOS subthreshold logic gate is developed. Although short-channel effects can increase P DC significantly, the balanced transistor strength will reduce PDC more efficiently by improving the consistency of transistor strength between P-JLDGFET and N-JLDGFET. Being similar to DIBL, the minimum channel length that corresponds to the allowable maximum PDC in designing the low-power logic gate can be determined according to the scaling theory. Although the inverter (INV) may act as the fundamental building unit for the logic circuits due to its least gate counts among INV, nand , and nor , it consumes the most PDC among these logic gates. The minimum DC power PDC,min can be obtained by tuning the gate work-function, which ensures the equal transistor strength between P-JLDGFET and N-JLDGFET. Both of the variability and sensitivity induced by the process parameters are also accounted for in developing PDC model.

A New Device-Parameter-Oriented DC Power Model for Symmetric Operation of Junctionless Double-Gate mosfet Working on Low-Power CMOS Subthreshold Logic Gates

This paper proposes a novel vertical MOSFET with the middle partial insulation and block oxide (bMPI) structure for 1T-DRAM application. The bMPI 1T-DRAM can increase the pseudo-neutral region due to the bMPI under the vertical channel and its device sensing current window is improved about 95% when compared to the planer bMPI 1T-DRAM. Because of the double gate structure, the proposed device has great gate controllability; hence, it can reduce the short-channel effects and enhance the electrical characteristics.

A novel vertical MOSFET with bMPI structure for 1T-DRAM application

In this paper, we propose a source-tied vertical MOSFET (STVMOS) by using 3-D simulation. The characteristics of STVMOS are not only similar to the SOI vertical MOSFET (SOI-VMOS), but also have much better thermal reliability. According to TCAD simulation results, we have achieved 70 mV/decade S.S., 145 mV/V DIBL, and more than 109 I ON /I OFF current ratio.

A 3-D simulation study of a novel vertical MOSFET with source-tied (STVMOS)

We present a non-traditional CMOS inverter composed a junctionless (JL) NMOSFET and an N+-N−-P transistor which with simple process and high integration density in this paper. In the non-traditional CMOS inverter the JL NMOSFET serves as driver and the N+-N−-P transistor serves as load, respectively. Based on the measurement date of the N+-N−-P transistor published, we draw the load line of the non-traditional CMOS inverter and we found out that the N+-N−-P transistor can be used in the COMS circuit to advance the issues of the conventional CMOS today. Besides, the area reduced more than 46.1% are also be achieved.

Characterization for novel non-traditional CMOS inverter composed of a junctionless NMOSFET and a gated N + -N − -P transistor

In this study, junctionless technology employed for fabricating pseudo tri-gate vertical (PTGV) MOSFETs is proposed and the RF/analog performance is also investigated and demonstrated. According to simulation results, the excellent performances such as high transconductance (g m ), high cut-off frequency (ƒ T ), and high transconductance generation factor (g m /I d ) are achieved. The numerical results also provide a prediction of an 8nm gate length PTGV and JPTGV for RF applications.

Study of junctionless pseudo tri-gate vertical MOSFETs for RF/analog applications

A new planar-type body-connected FinFET structure produced by the isolation-last self-align process is demonstrated and characterized by using three-dimensional (3-D) numerical simulations. The new process step first defines the gate region and then the active region, thus it can achieve fully self-alignment undoubtedly. Besides, due to the isolation-last process (ILP), an additional body region (ABR) is exhibited under the gate region thereby improving the device electrical characteristics and the subthreshold properties. Its DIBL and subthreshold swing becomes better compared with its counterpart because the lower source/drain resistance and the wider device effective-width can be obtained. For the same reason, this new device shows a higher transconductance (G M ) behavior. And its drain conductance (G D ) also maintains a good electrical performance with no kink effect compared with the planar-type single top-gate FinFET. With ABR under the gate layer, the lattice temperature is decreased and the thermal instability is alleviated compared with its counterpart.

Yu-Che Chang

Papers

A novel vertical MOSFET with bMPI structure for 1T-DRAM application

A 3-D simulation study of a novel vertical MOSFET with source-tied (STVMOS)

Characterization for novel non-traditional CMOS inverter composed of a junctionless NMOSFET and a gated N + -N − -P transistor

Study of junctionless pseudo tri-gate vertical MOSFETs for RF/analog applications

A novel planar-type body-connected FinFET device fabricated by self-align isolation-last process