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Yu-ming Zhang

Bio: Yu-ming Zhang is an academic researcher from Xidian University. The author has contributed to research in topics: MOSFET & Threshold voltage. The author has an hindex of 4, co-authored 16 publications receiving 67 citations.

Papers
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Journal ArticleDOI
TL;DR: In this paper, the interfacial characteristics of Al/Al2O3/ZnO/n-GaAs metal-oxide-semiconductor (MOS) capacitor are investigated.
Abstract: The interfacial characteristics of Al/Al2O3/ZnO/n-GaAs metal—oxide—semiconductor (MOS) capacitor are investigated. The results measured by X-ray photoelectron spectroscopy (XPS) and high-resolution transmission electron microscopy (HRTEM) show that the presence of ZnO can effectively suppress the formations of oxides at the interface between the GaAs and gate dielectric and gain smooth interface. The ZnO-passivated GaAs MOS capacitor exhibits a very small hysteresis and frequency dispersion. Using the Terman method, the interface trap density is extracted from C–V curves. It is found that the ZnO layer can effectively improve the interface quality

28 citations

Journal ArticleDOI
Yuchen Li1, He-Ming Zhang1, HuiYong Hu1, Yu-ming Zhang1, Bin Wang1, Chunyu Zhou1 
TL;DR: In this paper, a simple analytical model for DG-TFET gate threshold voltage was built by solving quasi-two-dimensional Poisson equation in Si film, as a function of the drain voltage, the Si layer thickness, the gate length and the gate dielectric.
Abstract: The tunnel field-effect transistor (TFET) is a potential candidate for the post-CMOS era. As one of the most important electrical parameters of a device, double gate TFET (DG-TFET) gate threshold voltage was studied. First, a numerical simulation study of transfer characteristic and gate threshold voltage in DG-TFET was reported. Then, a simple analytical model for DG-TFET gate threshold voltage V TG was built by solving quasi-two-dimensional Poisson equation in Si film. The model as a function of the drain voltage, the Si layer thickness, the gate length and the gate dielectric was discussed. It is shown that the proposed model is consistent with the simulation results. This model should be useful for further investigation of performance of circuits containing TFETs.

13 citations

Journal ArticleDOI
TL;DR: In this article, the magnetic properties of 6H-SiC doped with transition metal (TM) atoms are calculated using the density functional theory method (DFT), and it is shown that TM doped in a 6HSiC host may have both magnetic and nonmagnetic states.
Abstract: Magnetic properties of 6H-SiC doped with transition metal (TM) atoms are calculated using the density functional theory method (DFT). It is shown that TM doped in a 6H-SiC host may have both magnetic and nonmagnetic states. From the figures of their density of states (DOS) and partial density of states (PDOS) and to compare the energy differences between ferromagnetic and nonmagnetic states, we demonstrate that Cr and Mn-doped 6H-SiC emerge a half-metallic ferromagnetic state, Co and Ni-doped 6H-SiC create very little magnetic features, while Fe-doped 6H-SiC is in the nonmagnetic state. We also calculate the energy differences between ferromagnetic and antiferromagnetic of Cr, Mn and Fe-doped 6H-SiC in the doping concentration (8.34%). It is found that the energy of the antiferromagnetic state is lower than that of the ferromagnetic state.

8 citations

Journal ArticleDOI
Bin Lu1, Hongliang Lu1, Yu-ming Zhang1, Yimen Zhang1, Xiaoran Cui1, Chengji Jin1, Chen Liu1 
TL;DR: An improved analytical model of theChannel surface potential in the tunnel field effect transistors is established with modified boundary conditions considering the source and drain depletion widths, avoiding the deviation of the channel potential and the overestimate on the electric field.

7 citations


Cited by
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Journal ArticleDOI
18 May 2018
TL;DR: In this article, the surface passivation on III-V semiconductors was reviewed and compared, and it was shown that several passivation methods can lead to a perfectly clean surface, but only a few methods can be considered for actual device integration due to their effectiveness and simplicity.
Abstract: The III-V compound semiconductor, which has the advantage of wide bandgap and high electron mobility, has attracted increasing interest in the optoelectronics and microelectronics field. The poor electronic properties of III-V semiconductor surfaces resulting from a high density of surface/interface states limit III-V device technology development. Various techniques have been applied to improve the surface and interface quality, which cover sulfur-passivation, plasmas-passivation, ultrathin film deposition, and so on. In this paper, recent research of the surface passivation on III-V semiconductors was reviewed and compared. It was shown that several passivation methods can lead to a perfectly clean surface, but only a few methods can be considered for actual device integration due to their effectiveness and simplicity.

53 citations

Journal ArticleDOI
TL;DR: ZnO surface passivation of a GaAs (100) substrate is investigated using an atomic layer deposition (ALD) process to prepare an ultrathin ZnO layer prior to ALD-HfO2 gate dielectric deposition to suppress the trapping of carriers in oxide defects with energies near the valence band edge of GaAs.
Abstract: We investigated ZnO surface passivation of a GaAs (100) substrate using an atomic layer deposition (ALD) process to prepare an ultrathin ZnO layer prior to ALD-HfO2 gate dielectric deposition. Significant suppression of both Ga-O bond formation near the interface and As segregation at the interface was achieved. In addition, this method effectively suppressed the trapping of carriers in oxide defects with energies near the valence band edge of GaAs. According to electrical analyses of the interface state response on p- and n-type GaAs substrates, the interface states in the bottom half of the GaAs band gap were largely removed. However, the interface trap response in the top half of the band gap increased somewhat for the ZnO-passivated surface.

34 citations

Journal ArticleDOI
TL;DR: In this paper, a new analytical model for the gate threshold voltage of a dual-material double-gate (DMDG) tunnel field effect transistor (TFET) was derived by solving the quasi-two-dimensional Poisson's equation in the lightly doped Si film.
Abstract: A new analytical model for the gate threshold voltage ($$V_\mathrm{TG}$$VTG) of a dual-material double-gate (DMDG) tunnel field-effect transistor (TFET) is reported. The model is derived by solving the quasi-two-dimensional Poisson's equation in the lightly doped Si film and employing the physical definition of $$V_\mathrm{TG}$$VTG. A numerical simulation study of the transfer characteristics and $$V_\mathrm{TG}$$VTG of a DMDG TFET has been carried out to verify the proposed analytical model. In the numerical calculations, extraction of $$V_\mathrm{TG}$$VTG is performed based on the transconductance change method as already used for conventional metal---oxide---semiconductor FETs (MOSFETs). The effects of gate length scaling, Si film thickness scaling, and modification of the gate dielectric on $$V_\mathrm{TG}$$VTG are reported. The dependence of $$V_\mathrm{TG}$$VTG on the applied drain bias is investigated using the proposed model. The proposed model can predict the effect of variation of all these parameters with reasonable accuracy.

27 citations

Journal ArticleDOI
TL;DR: In this paper, a hetero-dielectric buried oxide vertical tunnel held effect transistor (HDB VTFET) was used to obtain the superior improvement in terms of different RF and linearity.
Abstract: This work realises a hetero-dielectric buried oxide vertical tunnel held effect transistor (HDB VTFET) and investigates its radio frequency (RF) and linearity characteristics. First time, the concept of hetero-dielectric buried oxide (BOX) in VTFET is used to obtain the superior improvement in terms of different RF and linearity hgure of merits such as C gs , C gd , C gg , f T , Gain Bandwidth Product (GBP), t, Transconductance Frequency Product (TFP), Transconductance Generation Factor (TGF), g m2 , g m3 , VIP 2 , VIP 3 , IIP 3 , IMD 3 and 1-dB compression point. Also, the influence of HfO2 BOX length scaling on these FOMs is analysed. The results reveal that the HDB VTFET can be a promising contender to replace bulk metal-oxide semiconductor held-effect transistors in analogue/mixed signal system-on-chip and high-frequency microwave applications and the accuracy of this device is validated by TCAD Sentaurus simulator.

25 citations

Journal ArticleDOI
TL;DR: In this paper, a generalized 2D analytical model of gate threshold voltage for multiple material gate tunneling FET (TFET) structures is derived, which includes the effect of gate and drain bias, gate material workfunction, oxide thickness, silicon film thickness, gate dielectric, and other device parameters.
Abstract: A generalized 2-D analytical model of gate threshold voltage for multiple material gate Tunneling FET (TFET) structures is derived. The model can also be used for calculating threshold voltage of a single metal gate TFET. Surface potential model of a triple material double gate TFET has been developed by applying Gauss's law in the device. From the potential model, physics-based model of gate threshold voltage has been derived by exploring the transition between linear to quasi-exponential dependence of drain current on applied gate bias. The model includes the effect of gate and drain bias, gate material workfunction, oxide thickness, silicon film thickness, gate dielectric, and other device parameters. The accuracy of the proposed model is verified by comparing the results predicted by the proposed model to the results of the numerical model developed in Silvaco, Atlas.

24 citations