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Yu-Pin Hsu

Bio: Yu-Pin Hsu is an academic researcher from Rensselaer Polytechnic Institute. The author has contributed to research in topics: Instrumentation amplifier & RF power amplifier. The author has an hindex of 4, co-authored 13 publications receiving 49 citations.

Papers
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Journal ArticleDOI
TL;DR: The shorter sampling time of 26ms every 16s for the proposed FOCV MPPT method reduces the long charging tail required to refresh the sampling capacitor, resulting in a an improved average efficiency of 82.2% for the thermal harvester.
Abstract: This paper presents a thermal/RF hybrid energy harvester. The energy harvesting system can scavenge energy from a thermoelectric generator (TEG) and a radio-frequency (RF) energy source simultaneously, and deliver the combined power to a single load. Two techniques are employed in the system to increase the end-to-end efficiency; the rectifying-combination technique is proposed to eliminate the power loss associated with a dedicated AC-DC converter before the combiner and an improved fractional open-circuit voltage (FOCV) maximum power tracking (MPPT) is considered for a high average efficiency. A dynamic power path control extracts the maximum RF power from a cross-coupled differential rectifier, and also behaves as an AC/DC energy combiner. The thermal/RF harvester system achieves a measured peak end-to-end power conversion efficiency (PCE) of 63.4%. The shorter sampling time of 26ms every 16s for the proposed FOCV MPPT method reduces the long charging tail required to refresh the sampling capacitor, resulting in a an improved average efficiency of 82.2% for the thermal harvester. Fabricated in 0.18 $\mu \text{m}$ CMOS technology, the prototype operates at a thermal input voltage ranging from 40 mV to 400 mV and an RF power from −18 dBm to −3 dBm and delivers an output voltage of 1.8 V. The total area of the fabricated circuit prototype is 1.22 mm2.

25 citations

Journal ArticleDOI
TL;DR: This brief presents a power-efficient, highly linear front-end (FE) integrated circuit (IC) for electrocardiogram (ECG) acquisition applications that is capable of detecting high-fidelity ECG waveforms.
Abstract: This brief presents a power-efficient, highly linear front-end (FE) integrated circuit (IC) for electrocardiogram (ECG) acquisition applications. Compared to typical FE architectures, the proposed FE uses only one bandpass instrumentation amplifier (IA) to reduce the chip area and dc power consumption. To achieve high linearity, the bandpass IA is composed of a high-gain two-stage amplifier in a capacitive-feedback configuration. Miller compensation and the class-AB output stage are utilized to incorporate the filtering and buffering functions within the IA without the need for additional circuit stages. The FE IC is fabricated in 0.13- ${ \mu }\text{m}$ CMOS technology, and occupies only a 0.16-mm2 chip area. The measured input-referred noise is 3.2 ${ \mu }$ Vrms with a midband gain of 34.6 dB, and a bandwidth that extends from 0.9 to 350 Hz. A total harmonic distortion of −65 dB is measured at an input signal of 5.5 mV $_{{pp}}$ , with a dc power consumption of 1.8 ${\mu }\text{W}$ . In a real-time measurement, the proposed FE IC is capable of detecting high-fidelity ECG waveforms.

21 citations

Journal ArticleDOI
TL;DR: In real-time Electrocardiogram (ECG), Electromyography (EMG), and Electroencephalography (EEG) measurements, high-fidelity waveforms are acquired using the proposed FE IC, validating the system’s reconfigurability and high-linearity.
Abstract: This paper presents a reconfigurable front-end (FE) circuit for acquiring various low-frequency biomedical signals. An energy and area-efficient tunable filter is proposed for adapting the FE bandwidth to the signal of interest. The filter is designed using a switched-R-MOSFET-C (SRMC) technique to realize the needed ultra-low cutoff frequency. An 8-bit SAR ADC, following the filter, quantizes the signal, while the SAR control logic is re-used to accurately program the filter bandwidth from 40 Hz to 320 Hz with a 40 Hz step. The prototype chip includes the complete FE system, formed of an instrumentation amplifier (IA), a programmable-gain amplifier (PGA), and the proposed tunable filter followed by the SAR ADC. Implemented in 0.13 $\mu \text{m}$ CMOS technology, the IC occupies a 0.6 mm2 active area while consuming 6.3 $\mu \text{W}$ dc power from a 2-V supply. Measurement results show a FE gain range of 43–55 dB with an integrated input-referred noise ( ${V_{\text {IRN}}}$ ) of 3.45 $\mu V_{\text {rms}}$ , a 66 dB dynamic range (DR), and a total-harmonic distortion (THD) of −68 dB at an input amplitude of 6 $\text{m}V_{PP}$ . The effective number of bits (ENOB) for the ADC is 7.921 bits at 1-kS/s. In real-time Electrocardiogram (ECG), Electromyography (EMG), and Electroencephalography (EEG) measurements, high-fidelity waveforms are acquired using the proposed FE IC, validating the system’s reconfigurability and high-linearity.

21 citations

Journal ArticleDOI
TL;DR: Results show that the impedance tuning mechanism can extend the optimal frequency range where the efficiency is higher than 80% of its peak value from 150 MHz (800–950 MHz) for the case without tuning to 220 MHz (780 MHz–1 GHz) when the impedance is adjusted using the control loop.
Abstract: This paper presents an RF-DC converter integrated circuit (IC) with ~307- $\mu \text{W}$ output power capable of powering individual health monitoring systems. The IC is designed with an on-chip adaptive impedance matching network to accommodate a wide input RF power variation and extend the operating frequency range. The system is composed of an antenna, an adaptive impedance matching network, a three-stage full-wave RF-DC rectifier, and a low-power digital control loop. A 5-bit successive-approximation-register analog-to-digital converter (ADC) is employed to monitor the dc output voltage and tune a 4-bit binary-weighted capacitor array in the matching network through the control loop. The complete system is designed and fabricated in standard 0.13- $\mu \text{m}$ CMOS technology. The post-simulated power consumption of the 5-bit ADC and digital control loop is 208 and 87 nW, respectively. Measurement results show that the impedance tuning mechanism can extend the optimal frequency range where the efficiency is higher than 80% of its peak value from 150 MHz (800–950 MHz) for the case without tuning to 220 MHz (780 MHz–1 GHz) when the impedance is adjusted using the control loop. The system achieves a measured end-to-end peak efficiency of 29.3% and is able to deliver an output power higher than 300 $\mu \text{W}$ with an output voltage and current of 1.75 V and 175.4 $\mu \text{A}$ , respectively. The active chip area is 0.17 mm2 including the control loop and ADC.

15 citations

Proceedings ArticleDOI
01 Aug 2016
TL;DR: A novel tuning mechanism is proposed to automatically adjust the impedance of the matching network, which can effectively improve the power efficiency of the system by 47% compared to the case without tuning.
Abstract: This paper presents a high-efficiency RF powering system, suitable for individual health monitoring applications. The system is composed of an antenna, an impedance matching network, and a two-stage full-wave RF-DC rectifier. A novel tuning mechanism is proposed to automatically adjust the impedance of the matching network. This mechanism can effectively improve the power efficiency of the system by 47% compared to the case without tuning. For the adaptive impedance, only a 5-bits binary weighted capacitor bank is required in the matching network. The complete system, designed in a standard 0.13μm CMOS technology, converts a −6dBm 915MHz RF signal to a 1.7V DC voltage with an output current of 85μΑ. The simulated maximum power efficiency of the complete RF harvester is 66%.

8 citations


Cited by
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01 Jan 2016
TL;DR: The design of analog cmos integrated circuits is universally compatible with any devices to read and is available in the book collection an online access to it is set as public so you can download it instantly.
Abstract: Thank you for downloading design of analog cmos integrated circuits. Maybe you have knowledge that, people have look hundreds times for their chosen books like this design of analog cmos integrated circuits, but end up in malicious downloads. Rather than enjoying a good book with a cup of coffee in the afternoon, instead they juggled with some harmful virus inside their computer. design of analog cmos integrated circuits is available in our book collection an online access to it is set as public so you can download it instantly. Our digital library spans in multiple countries, allowing you to get the most less latency time to download any of our books like this one. Kindly say, the design of analog cmos integrated circuits is universally compatible with any devices to read.

1,038 citations

Proceedings Article
01 Jan 2010
TL;DR: In this article, a low power boost converter for thermoelectric energy harvesting that demonstrates an efficiency that is 15% higher than the state-of-the-art for voltage conversion ratios above 20.
Abstract: This paper presents a low power boost converter for thermoelectric energy harvesting that demonstrates an efficiency that is 15% higher than the state-of-the-art for voltage conversion ratios above 20. This is achieved by utilizing a technique allowing synchronous rectification in the discontinuous conduction mode. A low-power method for input voltage monitoring is presented. The low input voltage requirements allow operation from a thermoelectric generator powered by body heat. The converter, fabricated in a 0.13 μm CMOS process, operates from input voltages ranging from 20 mV to 250 mV while supplying a regulated 1 V output. The converter consumes 1.6 (1.1) μW of quiescent power, delivers up to 25 (175) μW of output power, and is 46 (75)% efficient for a 20 mV and 100 mV input, respectively.

412 citations

Journal ArticleDOI
TL;DR: This article designs a receiver circuit for processing SWIPT signals, which is designed with the aim of minimizing the circuit complexity and power consumption for information decoding, and analyzes the proposed receiver circuit to derive the closed-form expression for the energy harvesting efficiency and the frequency response of the communication signal.
Abstract: In this article, we propose a novel simultaneous wireless information and power transfer (SWIPT) scheme for the Internet of Things (IoT). Different from the conventional power splitting (PS) and time switching (TS) schemes, the proposed scheme sends the wireless power via the unmodulated high-power continuous wave (CW) and transmits information by using a small modulated signal in order to reduce the interference and to enhance the power amplifier efficiency. We design a receiver circuit for processing such SWIPT signals, which is designed with the aim of minimizing the circuit complexity and power consumption for information decoding. This goal is achieved by first rectifying the received signal and then splitting the power and information signals. We analyze the proposed receiver circuit and derive the closed-form expression for the energy harvesting efficiency and the frequency response of the communication signal. We have implemented the proposed receiver circuit and built the real-time testbed for experimenting with simultaneous transmission of information and power. By experiments, we have verified the correctness of the receiver circuit analysis and shown the validity of the proposed SWIPT scheme.

66 citations

Journal ArticleDOI
TL;DR: In this article, the authors present a review of the previous articles and provide a proper division, performance method for selecting the appropriate algorithm, which explains the performance, application, advantages and disadvantages of algorithms to be a good reference for selecting an appropriate algorithm.
Abstract: One of the most available energy sources in the world is solar energy, while in the category of renewable and nonrenewable energies is in the first group. Power generation of a photovoltaic (PV) system is a technique which is possible by using solar cells. Since photovoltaic systems cannot force solar cells to operate at MPP, a controller is needed to do so. If the controller can operate more accurately, or in other words, be optimized, the system will have an appropriate output. Many papers have been presented on maximum power point tracking algorithms. This paper intends to review the previous articles and provide a proper division, performance method. This explains the performance, application, advantages and disadvantages of algorithms to be a good reference for selecting the appropriate algorithm. Algorithms in this paper are divided into four categories methods based on measurement, calculation, intelligent schemes and hybrid schemes. The exhibition of new algorithms and the optimization of previous algorithms have led to the number of articles in this field over the years. In order to review the methods a comparative table is also provided. Finally, a PV system has been controlled by using three algorithms P&O, IC and Fuzzy-PI. The outputs control signals from the MPPT have been applied by Boost and SEPIC converters, and the outputs have been compared. Simulations have been performed in MATLAB/Simulink software.

41 citations

Journal ArticleDOI
TL;DR: The shorter sampling time of 26ms every 16s for the proposed FOCV MPPT method reduces the long charging tail required to refresh the sampling capacitor, resulting in a an improved average efficiency of 82.2% for the thermal harvester.
Abstract: This paper presents a thermal/RF hybrid energy harvester. The energy harvesting system can scavenge energy from a thermoelectric generator (TEG) and a radio-frequency (RF) energy source simultaneously, and deliver the combined power to a single load. Two techniques are employed in the system to increase the end-to-end efficiency; the rectifying-combination technique is proposed to eliminate the power loss associated with a dedicated AC-DC converter before the combiner and an improved fractional open-circuit voltage (FOCV) maximum power tracking (MPPT) is considered for a high average efficiency. A dynamic power path control extracts the maximum RF power from a cross-coupled differential rectifier, and also behaves as an AC/DC energy combiner. The thermal/RF harvester system achieves a measured peak end-to-end power conversion efficiency (PCE) of 63.4%. The shorter sampling time of 26ms every 16s for the proposed FOCV MPPT method reduces the long charging tail required to refresh the sampling capacitor, resulting in a an improved average efficiency of 82.2% for the thermal harvester. Fabricated in 0.18 $\mu \text{m}$ CMOS technology, the prototype operates at a thermal input voltage ranging from 40 mV to 400 mV and an RF power from −18 dBm to −3 dBm and delivers an output voltage of 1.8 V. The total area of the fabricated circuit prototype is 1.22 mm2.

25 citations