Yuan Wang

Bio: Yuan Wang is an academic researcher from Fudan University. The author has contributed to research in topics: Field-programmable gate array & Logic synthesis. The author has an hindex of 3, co-authored 8 publications receiving 18 citations.

An FPGA configuration circuit used for fast and partial configuration

Abstract: An improved architecture used for FPGA's fast and partial configuration is proposed. It is designed based on a 32 bits wide data bus, which can be controlled by a set of instructions. A partial control register and an address decoding logic are added in this design. Multiple configuration interfaces could be connected in this architecture, making hardware updating fast and convenient. Comparing with Virtex Series FPGA's configuration architecture, produced by Xilinx Corp., which only can configure memory cells by frame, this new architecture could configure any single memory cell in FPGA, offering more flexible configuration operations.

A new configurable logic block with 4/5-input configurable LUT and fast/slow-path carry chain

Abstract: A new LUT and carry structure embedded in the configurable logic block of FPGA is proposed. The LUT is designed to support both 4-input and 5-input structures, which can be configured by users according to their needs without increasing the complexity of interconnect structures. We also develop a new carry chain structure with fast and slow carry paths. The circuit is fabricated in 0.13um 1P8M 1.2/2.5/3.3V Logic CMOS technology. The measured results show a correct function of 4/5-input LUT and a speedup in carry performance of nearly 3 times over current architecture.

BRAM-based asynchronous FIFO in FPGA with optimized cycle latency

Abstract: The design of BRAM-based FIFO in FPGA with high speed and low power consumption is presented. Meanwhile, the paper improves the design with optimized cycle latency to meet the requirements of instant and stability of state flag logic circuit design to support the high-performance FIFO. Moreover, two different types of address, B2G circuit and traveling-wave architecture accumulator are used to make the design with smaller area and lower power. Two more state flags are added to make it more practical to be controlled by users though expanding FIFO's functions. And it shows 11.9% faster in frequency and only 28.8% of the area of FIFO in literature. The proposed FIFO can work with the same frequency as high performance Virtex-IV.

Uniform routing architecture for FPGA with embedded IP cores

Abstract: A uniform routing architecture is presented, which offers CLB, IOB and IP Cores an identical routing resource. At the same time, some method is adopted to optimize routing performance. With all unidirectional segmented lines and long lines with inserted tap buffers, this architecture is up to 9.8% faster compared with long lines without inserted buffers and on average 14.9% over bidirectional lines. Simulation results demonstrate our idea1.

A Flexible Bit-Stream Level Evolvable Hardware Platform Based on FPGA

Abstract: A flexible bit-stream level evolvable hardware (EHW) platform is proposed in order to efficiently utilize the programmable logic resources of FPGA when evolving digital circuits. This platform is based on the FuDan FPGA device. An adaptive variable-size look-up-table (LUT) array structure is proposed with the optimal Genetic Algorithm to evolvable circuits. The experiment results showed that the proposed platform is more flexible, and it not only can make good use of FPGA logic resources, but also has a quick evolving speed.

Area-oriented technology mapping for LUT-based logic blocks

Abstract: Abstract One of the main aspects of logic synthesis dedicated to FPGA is the problem of technology mapping, which is directly associated with the logic decomposition technique. This paper focuses on using configurable properties of CLBs in the process of logic decomposition and technology mapping. A novel theory and a set of efficient techniques for logic decomposition based on a BDD are proposed. The paper shows that logic optimization can be efficiently carried out by using multiple decomposition. The essence of the proposed synthesis method is multiple cutting of a BDD. A new diagram form called an SMTBDD is proposed. Moreover, techniques that allow finding the best technology mapping oriented to configurability of CLBs are presented. In the experimental section, the presented method (MultiDec) is compared with academic and commercial tools. The experimental results show that the proposed technology mapping strategy leads to good results in terms of the number of CLBs.

Design and implementation of the configuration circuit for FDP FPGA

Abstract: This paper presents a configuration circuit used in the FDP (FDP: Fu Dan Programmable device) FPGA chip. This circuit could write configuration data into FDP and read back data from FDP successfully. Comparing with Xilinx Virtex Series FPGA chips, the smallest configuration section of which is one data-frame, the proposed circuit could write each single memory cell in FDP, providing more flexible configuration operations. A standard configuration interface, Serial Peripheral Interface (SPI), is added in this circuit to replace using the expensive Xilinx Platform configuration Flash PROMs. A group of high precise sensitive amplifiers is adopted in this configuration circuit, which are used to magnify the read back data values. Through a novel write/read asynchronous FIFO structure in FDP, which divides the external interface and internal configuration circuit into two clock domains, designers could set the external clock and internal clock separately. Basic functions of the configuration circuit have been correctly verified by Altera DE2 development board platform. The post layout simulation results indicate via this configuration circuit, each data frame in FDP could be written in 4 mus, and could be read back in 5 mus. The total configuration time of FDP chip is about 6.5 ms.

A self-reconfiguring platform

Abstract: A self-reconfiguring platform is reported that enables an FPGA to dynamically reconfigure itself under the control of an embedded microprocessor. This platform has been implemented on Xilinx Virtex II tm and Virtex II Pro tm devices. The platform's hardware architecture has been designed to be lightweight. Two APIs (Application Program Interface) are described which abstract the low level configuration interface. The Xilinx Partial Reconfiguration Toolkit (XPART), the higher level of the two APIs, provides methods for reading and modifying select FPGA resources. It also provides support for relocatable partial bitstreams. The presented self-reconfiguring platform enables embedded applications to take advantage of dynamic partial reconfiguration without requiring external circuitry.

A SPI FLASH-based FPGA dynamic reconfiguration method

Abstract: To make the FPGA configuration more flexible and easier, this article designs a SPI FLASH-based FPGA dynamic reconfiguration method according to the principle of FPGA configuration. In the paper, some of the key technologies in software design are analyzed and solved. Besides, the design has been verified on the hardware platform as well. The results show that this design is reasonably practicable and has achieved the design requirements of dynamic reconfiguration.

Hardware implementation of a low power SD card controller

Abstract: Technical innovation drives the low power consumption requirements in ASIC design. This paper presents a SD card controller, in which two asynchronous units (BIU and CIU) are included for lower power structure. Adding low power mode to finite state machine makes this controller to shut down if no data or command is transferring for a long time. Only one FIFO is used to store temporary data in order to save area, it is still simplified though add some control logics. These modified structures are specifically implemented for low power applications, and hardware cost is reduced at the same time. FPGA prototyping results show the correctness of the proposed design, and it is synthesized by CSMC 180nm CMOS technology process with a clock frequency of 100 MHz, dynamic power consumption of 8.2223mW and 12.2K equivalent logic gates.