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Yuan-Yuan Wang

Bio: Yuan-Yuan Wang is an academic researcher from Soochow University (Suzhou). The author has contributed to research in topics: Cache & Low-power electronics. The author has an hindex of 1, co-authored 1 publications receiving 6 citations.

Papers
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Proceedings ArticleDOI
01 Oct 2012
TL;DR: In this article, a new 6T-SRAM cell structure of nano-scale technology for low power application is presented, which is closed to the traditional 6T cell, and power consumption is reduced by 22.45% during the write operation.
Abstract: Power consumption is becoming a pressing issue in cache design. And SRAM (static random access memory) cells occupy a large area of the cache. Recent research shows that SRAM's power dissipation contributes to a key part of the whole chip power consumption. By using separate write and read operation, this paper presents a new 6T-SRAM cell structure of nano-scale technology for low power application. Simulation results with standard 65nm CMOS (complementary metal oxide semiconductor) technology show that the speed is closed to the traditional 6T cell, power consumption is reduced by 22.45% during the write operation of 0. Particularly, in idle mode this structure maintains its data with the help of leakage current and positive feedback, which can greatly improves the power consumption of the nano-scale SRAM.

8 citations


Cited by
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Proceedings ArticleDOI
04 Jan 2016
TL;DR: The proposed static random access memory (SRAM) design furnishes an approach towards curtailing the hold power dissipation by using a tail transistor which aids in limiting the short circuit power Dissipation by disrupting the direct connection between supply voltage and ground.
Abstract: The present world aims in designing low power devices due to the rampant usage of portable battery powered gadgets. The proposed static random access memory (SRAM) design furnishes an approach towards curtailing the hold power dissipation. The design uses a tail transistor which aids in limiting the short circuit power dissipation by disrupting the direct connection between supply voltage and ground. This tail transistor also brings down the sub threshold current by providing stacking effect, which subsequently reduces hold power dissipation. A supply voltage of 0.8V is used which makes it eligible for low power applications. The designed SRAM cell has single ended write and read operations and is simulated using Cadence 45nm CMOS technology. Statistical and corner analysis is also performed for the proposed design for its robustness. The proposed SRAM cell has a hold power dissipation of 4.74154pW which is much less as compared to the standard 6T SRAM cell.

12 citations

Proceedings ArticleDOI
01 Dec 2014
TL;DR: In this article, the authors have designed SRAM cell using double gate FinFET to minimize short channel effects, they have designed 8×8 memory array using the best configuration using the Cadence virtuoso tool.
Abstract: Energy efficient and low power circuit designing has become challenging for many years Now a day in Modern 1C designing, SRAM design somewhat significant because it will occupy more space on a die and consumes large fraction of energy of the chip Scaling of conventional CMOS circuit leads to have short channel effects due to which, effect such as drain induced barrier lowering, hot electron effect, punch through etc takes place and hence leakage power increases in the transistor In this paper, to minimize short channel effects, we have designed SRAM cell using double gate FinFET FinFET may be the most promising device in the LSI (large scale integration) circuits because it realizes the self-aligned double-gate structure easily Simulation is performed with Cadence virtuoso tool The low power in SRAM is achieved by driving the two gates of FinFET independently We have designed some SRAM circuits using FinFET and compared their results After that, using the best configuration we have designed 8×8 memory array

3 citations

Journal ArticleDOI
TL;DR: This paper deals with design of low power static random-access memory cells and peripheral circuits for standalone RAMs, in 32nm focusing on stable operation and reduced leakage power dissipation.
Abstract: Continuous scaling of the transistor size and reduction of the operating voltage has led to a significant performance improvement of integrated circuits. Low power consumption and smaller area are the most important criteria for the fabrication of DSP systems. Static random access memories (SRAMs) consist of almost 90% of very large scale integrated (VLSI) circuits. The ever-increasing demand for larger data storage capacity has driven the fabrication technology and memory development toward more compact design rules and, consequently, toward higher storage densities. This paper deals with design of low power static random-access memory (RAM) cells and peripheral circuits for standalone RAMs, in 32nm focusing on stable operation and reduced leakage power dissipation. The work is carried out on Tanner Tool version 13 at 32nm technology.

1 citations

Journal ArticleDOI
TL;DR: Comparing leakage power, dynamic power and static power at 90 nm technology and write delay, read delay at both 90-nm and 45-nm technology in nine transistors (9 t), eight transistor (8 t) and six transistor (6 T) sram cell.

1 citations

Journal Article
TL;DR: This paper involves the integration of column decoder and multiplexer into a power efficient column select and use of twisted bitlines instead of normal bitlines and replacing linear sense amplifier with latch based sense amplifier.
Abstract: SRAM cells are widely used as cache memory in most of the devices now a days. Design of SRAM with low power and high efficiency has been a difficult task which is continuously being upgraded. In this paper we came out with a novel method to reduce the power consumption of SRAM cell by combining most advanced technologies in the SRAM cell design. This paper involves the integration of column decoder and multiplexer into a power efficient column select and use of twisted bitlines instead of normal bitlines and replacing linear sense amplifier with latch based sense amplifier. In this project, standard 6T (6 transistors) are used by which the leakage current is drastically reduced and low power is achieved. The full custom layout of the SRAM was realized using Electric VLSI CAD tool, the DRC and LVS was verified using Electric VLSI CAD tool and the Simulation was verified using LTSpice tool. The final tapeout (GDS II) was done using Electric VLSI CAD tool. Keyword-CMOS, SRAM, VLSI, Twisted Bitlines, LSA