Yue Chao

Bio: Yue Chao is an academic researcher from Hong Kong University of Science and Technology. The author has contributed to research in topics: CMOS & Phase noise. The author has an hindex of 7, co-authored 14 publications receiving 167 citations. Previous affiliations of Yue Chao include Qualcomm.

Analysis and Design of a 2.9-mW 53.4–79.4-GHz Frequency-Tracking Injection-Locked Frequency Divider in 65-nm CMOS

Abstract: A frequency-tracking technique is proposed to enhance the locking range of millimeter-wave (mmW) injection-locked frequency dividers (ILFDs). An improved model is introduced for direct-injection ILFDs, based on which both the phase and gain conditions are analyzed and discussed. Moreover, a method of admittance locus is applied to obtain the design intuition for optimization and to predict the locking range accurately. Finally, with the proposed model and design methodology, a frequency-tracking ILFD is designed and fabricated in a 65-nm CMOS process, which measures a locking range of 39.2% from 53.4 to 79.4 GHz while consuming 2.9 mW from an 0.8-V power supply, which corresponds to an FoM of 8.97 GHz/mW.

Analysis and Design of Wide-Band Millimeter-Wave Transformer-Based VCO and ILFDs

Abstract: Several transformer-based techniques are proposed to enhance the frequency tuning range of mm-wave voltage-controlled oscillators (VCOs) and the frequency locking range of injection-locked frequency dividers (ILFDs). Firstly, a switched-transformer VCO (ST-VCO) based on dual-band topology is proposed to increase the frequency tuning range. Secondly, transformer-distribution ILFDs (TD-ILFDs) are demonstrated to achieve much improved frequency locking range with compact chip area and low power consumption. Thirdly, the injection-saturation problem of ILFDs is identified, analyzed, and solved in this work. A VCO and three different TD-ILFDs are designed and fabricated in a 65 nm CMOS process. The proposed ST-VCO measures wide tuning range of 22.3% from 62.1 GHz to 78.3 GHz with phase noise of −112 dBc/Hz at 10 MHz offset while consuming 7.7 mW, corresponding to FoM and FoMT of −180.4 dBc/Hz and −187.4 dBc/Hz, respectively. The proposed 60-GHz TD-ILFDs measure locking range of 19.6 GHz (29.6%), 19.8 GHz (29.2%), and 3.8 GHz (6.1%) while consuming 1.44 mW, 1.44 mW, and 0.44 mW.

A Spur-and-Phase-Noise-Filtering Technique for Inductor-Less Fractional-N Injection-Locked PLLs

Abstract: A novel phase-noise-filtering technique based on phase-domain averaging is proposed to suppress the large injection spurs and poor high-frequency phase noise of inductor-less injection-locked phase-locked loops (IL-PLLs). Demonstrated using a 1.2-GHz fractional-N IL-PLL based on a capacitive-ring-coupled ring oscillator, wideband spur-and-phase-noise suppression of up to 20 dB is achieved allowing for phase noise as low as −146 dBc/Hz at 30-MHz offset with a 2-MHz resolution. This allows for an inductor-less alternative to LC-based PLLs in scaled-digital CMOS technologies. The 65-nm CMOS prototype improves 10-MHz phase noise from −115 to −135 dBc/Hz, injection spurs from −40.5 to −57 dB, and integrated jitter from 3.57 to 1.48 ps while occupying an area of 0.6 mm2 and consuming 19.8 mW from a 0.85-V supply, resulting in an FoM and FoMJitter of −163 and −223.6 dB, respectively.

Analysis and Design of a 14.1-mW 50/100-GHz Transformer-Based PLL With Embedded Phase Shifter in 65-nm CMOS

Abstract: A low-voltage and low-power 50/100-GHz transformer-based phase-locked loop (PLL) is implemented in a 65-nm CMOS technology. Consuming only 14.1 mW from a 0.6/1.2-V supply, the PLL measures phase noise of $-$ 90/ $-$ 84 dBc/Hz at 100-kHz offset and $-$ 94/ $-$ 88 dBc/Hz at 1-MHz offset at 49.7/99.4 GHz while occupying a core chip area of ${\hbox{0.39}}\ {\hbox{mm}}^{2}$ . Moreover, with an embedded phase shifter, the PLL output phase can be shifted by a 360 $^{\circ}$ range with an average resolution of 3.9 $^{\circ}$ and amplitude variation less than $\pm$ 0.1 dB, which makes it suitable for phased-array transceivers.

Transformer-based dual-band VCO and ILFD for wide-band mm-Wave LO generation

Abstract: Switched-transformer and transformer-distribution design techniques are proposed for wideband mm-Wave dual-band VCOs and ILFDs. Fabricated in a 65nm CMOS process, a dual-band VCO prototype measures a tuning range of 22.3% from 62.1GHz to 78.3GHz with a phase noise of -112.0dBc/Hz at 10MHz offset while consuming 7.7mW, corresponding to FoM and FoMT of -180.4dBc/Hz and -187.4dBc/Hz, respectively. A proposed ILFD prototype achieves locking range from 58GHz to 77.8GHz with 1.44mW power and FoM of 13.75GHz/mW. A cascade of the proposed VCO and ILFD is also demonstrated with an overall locking range of 15.7% from 62.1GHz to 73.3GHz.

The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES

Abstract: This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0

A 60 GHz Frequency Generator Based on a 20 GHz Oscillator and an Implicit Multiplier

Abstract: This paper proposes a mm-wave frequency generation technique that improves its phase noise (PN) performance and power efficiency. The main idea is that a fundamental 20 GHz signal and its sufficiently strong third harmonic at 60 GHz are generated simultaneously in a single oscillator. The desired 60 GHz local oscillator (LO) signal is delivered to the output, whereas the 20 GHz signal can be fed back for phase detection in a phase-locked loop. Third-harmonic boosting and extraction techniques are proposed and applied to the frequency generator. A prototype of the proposed frequency generator is implemented in digital 40 nm CMOS. It exhibits a PN of $-100\;\text{dBc/Hz}$ at 1 MHz offset from 57.8 GHz and provides 25% frequency tuning range (TR). The achieved figure-of-merit (FoM) is between 179 and 182 dBc/Hz.

A Highly Digital MDLL-Based Clock Multiplier That Leverages a Self-Scrambling Time-to-Digital Converter to Achieve Subpicosecond Jitter Performance

Abstract: This paper presents a mostly digital multiplying delay-locked loop (MDLL) architecture that leverages a new time-to-digital converter (TDC) and a correlated double-sampling technique to achieve subpicosecond jitter performance. The key benefit of the proposed structure is that it provides a highly digital technique to reduce deterministic jitter in the MDLL output with low sensitivity to mismatch and offset in the associated tuning circuits. The TDC structure, which is based on a gated ring oscillator (GRO), is expected to benefit other PLL/DLL applications as well due to the fact that it scrambles and first-order noise shapes its associated quantization noise. Measured results are presented of a custom MDLL prototype that multiplies a 50 MHz reference frequency to 1.6 GHz with 928 fs rms jitter performance. The prototype consists of two 0.13 μm integrated circuits, which have a combined active area of 0.06 mm 2 and a combined core power of 5.1 mW, in addition to an FPGA board, a discrete DAC, and a simple RC filter.

Low-Phase-Noise Wideband Mode-Switching Quad-Core-Coupled mm-wave VCO Using a Single-Center-Tapped Switched Inductor

Abstract: This paper describes a mode-switching quad-core-coupled millimeter-wave (mm-wave) voltage-controlled oscillator (VCO), using a single-center-tapped (SCT) switched inductor for extension of the frequency tuning range (FTR) and improvement of the phase noise (PN). The switches not only serve for in-phase coupling among the VCO cores but also can modify the equivalent tank inductance suitable for coarse frequency tuning. The frequency gaps between the multi-resonant frequencies are controlled by the common-mode (CM) inductance that is precisely set by the lithography fabrication. Together with the tiny varactors for fine frequency tuning, a wide and continuous FTR can be achieved. It is analytically shown that tiny switches (i.e., small parasitic capacitance) for mode selection are adequate to avoid bimodal oscillation, synchronize the VCO cores against resonance frequency mismatches, and prevent PN degradation. A symmetrical layout of SCT switched inductor also aids the VCO to be immune to magnetic pulling. Prototyped in 65-nm CMOS, the VCO exhibits a 16.5% FTR from 42.9 to 50.6 GHz. The PN at 46.03 GHz is −113.1 dBc/Hz at 3-MHz offset, corresponding to a figure-of-merit (FoM) of 183.6 dBc/Hz. The die size is 0.039 mm2.

Analysis and Design of Ultra-Wideband mm-Wave Injection-Locked Frequency Dividers Using Transformer-Based High-Order Resonators

Abstract: A transformer-based high-order resonator is proposed to improve the locking range (LR) of the millimeter-wave injection-locked frequency dividers (ILFDs). The LR limitations on ILFDs are discussed, and the operating principles of the proposed high-order resonator are analyzed based on their flattened phase response. The inductive gain peaking technique and the tail current source requirement are further analyzed for low power considerations. Two chips are fabricated in a 65-nm CMOS process to implement the proposed techniques: the first one measures an LR of 62.9% from 27.9 to 53.5 GHz while consuming 5.8 mW from a 1-V power supply and the second chip achieves an LR of 62.7% from 32.4 to 61.9 GHz while consuming only 1.2 mW from a 0.42-V power supply. The best figure of merit can achieve up to 24.7 GHz/mW.