Y
Yue Zhang
Researcher at Beihang University
Publications - 83
Citations - 1981
Yue Zhang is an academic researcher from Beihang University. The author has contributed to research in topics: Spin-transfer torque & CMOS. The author has an hindex of 23, co-authored 79 publications receiving 1406 citations. Previous affiliations of Yue Zhang include Centre national de la recherche scientifique.
Papers
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Low Power Magnetic Full-Adder Based on Spin Transfer Torque MRAM
TL;DR: In this article, a novel magnetic fulladder (MFA) design based on perpendicular magnetic anisotropy (PMA) STT-MRAM is presented, which provides power efficiency and die area compared with conventional CMOS-only full adder (FA).
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Compact Model of Dielectric Breakdown in Spin-Transfer Torque Magnetic Tunnel Junction
You Wang,Hao Cai,Lirida Alves de Barros Naviner,Yue Zhang,Xiaoxuan Zhao,Erya Deng,Jacques-Olivier Klein,Weisheng Zhao +7 more
TL;DR: In this paper, the physical mechanisms of time-dependent dielectric breakdown (TDDB) in an oxide barrier were analyzed and an SPICE-compact model of the MTJ was proposed.
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Synchronous Non-Volatile Logic Gate Design Based on Resistive Switching Memories
Weisheng Zhao,Mathieu Moreau,Erya Deng,Yue Zhang,Jean-Michel Portal,Jacques-Olivier Klein,Marc Bocquet,Hassen Aziza,Damien Deleruyelle,Christophe Muller,Damien Querlioz,Nesrine Ben Romdhane,Dafiné Ravelosona,Claude Chappert +13 more
TL;DR: A theoretical investigation of synchronous NV logic gates based on RS memories (RS-NVL) is presented and special design techniques and strategies are proposed to optimize the structure according to different resistive characteristics of NVMs.
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Compact Model of Subvolume MTJ and Its Design Application at Nanoscale Technology Nodes
Yue Zhang,Bonan Yan,Wang Kang,Yuanqing Cheng,Jacques-Olivier Klein,Youguang Zhang,Yi Chen,Weisheng Zhao +7 more
TL;DR: In this paper, the authors investigated the origin of high spin-torque efficiency and gave a phenomenological theory to describe the critical current reduction due to the subvolume activation, and a compact model of nanoscale MTJ is developed and demonstrates a satisfactory agreement with experimental results.
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Magnetic Adder Based on Racetrack Memory
TL;DR: A new design of multi-bit magnetic adder (MA)-the basic element of arithmetic/logic unit for any processor-whose input and output data are stored in perpendicular magnetic anisotropy (PMA) domain wall (DW) racetrack memory (RM)-is presented in this paper.