Yuebing Jiang

Bio: Yuebing Jiang is an academic researcher from University of New Mexico. The author has contributed to research in topics: Image quality & Quantization (image processing). The author has an hindex of 7, co-authored 16 publications receiving 120 citations.

JPEG image compression using quantization table optimization based on perceptual image quality assessment

Abstract: We consider the use of perceptual image quality assessment for quantization table (QT) optimization for JPEG compression. For evaluating performance, we consider the use of the Structural Similarity Index (SSIM) for evaluating distortion in the compressed images. This leads to the study of rate-SSIM curves that replace the traditional use of rate-distortion curves based on the PSNR.

A dynamically reconfigurable architecture system for time-varying image constraints (DRASTIC) for motion JPEG

Abstract: We propose a dynamically reconfigurable system for time-varying image constraints (DRASTIC) for applications in video communications. DRASTIC defines a framework for both joint and independent optimization of dynamic power, image quality, and bitrate subject to different constraint scenarios. We demonstrate DRASTIC for intra-mode video encoding for MJPEG. However, since the DCT is critical component of most video coding standards, our approach can be extended to modern standards such as AVC (H.264), and emerging standards such as HEVC (H.265), and VP9. Based on a hardware–software co-design approach, we define a family of scalable 2D DCT hardware modules that are jointly optimized with the quality factor (in software). We generate a total of 1,280 configurations of which 841 were found to be Pareto optimal. For full 2D DCT calculation, the results indicate that the proposed method is DRASTIC mode implementation at least as good or significantly better than any previously published implementation. A scalable, real-time controller is used for selecting an appropriate configuration so as to meet time-varying constraints. The real-time controller is shown to satisfy the constraints of different communications modes (e.g., minimum dynamic power, maximum image quality, etc.) as well as to adapt to mode changes. Empirically, we have found that the DRASTIC controller adapts to meet the new constraints within five video frames of a mode change. Overall, the proposed approach yields significant savings over the use of comparable static architectures.

Dynamically reconfigurable DCT architectures based on bitrate, power, and image quality considerations

Abstract: We propose a dynamically reconfigurable DCT architecture system that can be used to optimize performance objectives while meeting real-time constraints on power, image quality, and bitrate. The proposed system can be dynamically reconfigured between 4 different modes: (i) minimum power mode, (ii) minimum bitrate mode, (iii) maximum image quality mode, and (iv) typical mode. The proposed system relies on the use of efficient DCT implementations that are parameterized by the word-length of the DCT transform coefficients and the use of different quantization quality factors. Optimal DCT architectures and quality factors are pre-computed on a training dataset. The proposed system is validated on the LIVE database using leave-one-out. From the results, it is clear that real-time constraints can be successfully met for the majority of the test images while optimizing for the 4 modes of operation.

A unified and pipelined hardware architecture for implementing intra prediction in HEVC

Abstract: The High Efficiency Video Coding (HEVC) standard can achieve significant improvements in coding performance over H.264/AVC. To achieve significant coding improvements in intra-predictive coding, HEVC relies on the use of an extended set of intra-prediction modes and prediction block sizes. This paper presents a unified hardware architecture for implementing all 35 intra-prediction modes that include the planar mode, the DC mode, and all angular modes for all prediction unit (PU) sizes ranging from 4 × 4 to 64 × 64 pixels. We propose the use of a unified reference sample indexing scheme that avoids the need for sample re-arrangement suggested in the HEVC reference design. The hardware architecture is implemented on a Xilinx Virtex 5 device (XC5VLX110T) for which we report power measurements, resource utilization, and the average number of required cycles per pixel.

System and methods for dynamic management of hardware resources

Abstract: A dynamically reconfigurable framework manages processing applications in order to meet time-varying constraints to select an optimal hardware architecture. The optimal architecture satisfies time-varying constraints including for example, supplied power, required performance, accuracy levels, available bandwidth, and quality of output such as image reconstruction. The process of determining an optimal solution is defined in terms of multi-objective optimization using Pareto-optimal realizations.

Devices, Methods, and Graphical User Interfaces for Messaging

Abstract: Electronic devices with improved methods and interfaces for messaging are disclosed, including improved ways to: acknowledge messages; edit previously sent messages; express what a user is trying to communicate; display private messages; synchronize viewing of content between users; incorporate handwritten inputs; quickly locate content in a message transcript; integrate a camera; integrate search and sharing; integrate interactive applications; integrate stickers; make payments; interact with avatars; make suggestions; navigate among interactive applications; manage interactive applications; translate foreign language text; combine messages into a group; and flag messages.

Algorithm and Architecture Design of the H.265/HEVC Intra Encoder

Abstract: Improved video coding techniques introduced in the H.265/High Efficiency Video Coding (HEVC) standard allow video encoders to achieve better compression efficiencies. On the other hand, the increased complexity requires a new design methodology able to face challenges associated with ever higher spatiotemporal resolutions. This paper presents a computationally scalable algorithm and its hardware architecture able to support intra encoding up to 2160p@30 frames/s resolution. The scalability allows a tradeoff between the throughput and the compression efficiency. In particular, the encoder is able to check a variable number of candidate modes. The rate estimation based on bin counting and the distortion estimation in the transform domain simplify the rate–distortion analysis and enable the evaluation of a great number of candidate intra modes. The encoder preselects candidate modes by the processing of $8\times 8$ predictions computed from original samples. The preselection shares hardware resources used for the processing of predictions generated from reconstructed samples. To support intra $4\times 4$ modes for the 2160p@30 frames/s resolution, the encoder incorporates a separate reconstruction loop. The processing of blocks with different sizes is interleaved to compensate for the delay of reconstruction loops. Implementation results show that the encoder utilizes 1086k gates and 52-kB on-chip memories for TSMC 90 nm. The main reconstruction loop can operate at 400 MHz, whereas the remaining modules work at 200 MHz. For 2160p@30 frames/s videos, the average BD-rate is 5.46% compared with that of the HM software.

An Introduction to Reconfigurable Systems

Abstract: Reconfigurability can be thought of as software-defined functionality, where flexibility is controlled predominately through the specification of bit patterns. Reconfigurable systems can be as simple as a single switch, or as abstract and powerful as programmable matter. This paper considers the generalization of reconfigurable systems as an important evolving discipline, bolstered by real-world archetypes such as field programmable gate arrays and software-definable radio (platform and application, respectively). It considers what reconfigurable systems actually are, their motivation, their taxonomy, the fundamental mechanisms and architectural considerations underlying them, designing them and using them in applications. With well-known real-world instances, such as the field programmable gate array, the paper attempts to motivate an understanding of the many possible directions and implications of a new class of system which is fundamentally based on the ability to change.

Modeling the Energy Consumption of the HEVC Decoding Process

Abstract: In this paper, we present a bit stream feature-based energy model that accurately estimates the energy required to decode a given High Efficiency Video Coding-coded bit stream. Therefore, we take a model from literature and extend it by explicitly modeling the in-loop filters, which was not done before. Furthermore, to prove its superior estimation performance, it is compared with seven different energy models from the literature. By using a unified evaluation framework, we show how accurately the required decoding energy for different decoding systems can be approximated. We give thorough explanations on the model parameters and explain how the model variables are derived. To show the modeling capabilities in general, we test the estimation performance for different decoding software and hardware solutions, where we find that the proposed model outperforms the models from the literature by reaching framewise mean estimation errors of less than 7% for software and less than 15% for hardware-based systems.

A generic psychovisual error threshold for the quantization table generation on JPEG image compression

Abstract: The quantization process is a main part of image compression to control visual quality and the bit rate of the image output. The JPEG quantization tables are obtained from a series of psychovisual experiments to determine a visual threshold. The visual threshold is useful in handling the intensity level of the colour image that can be perceived visually by the human visual system. This paper will investigate a psychovisual error threshold at DCT frequency on the grayscale image. The DCT coefficients are incremented one by one for each frequency order. Whereby, the contribution of DCT coefficients to the error reconstruction will be a primitive pyschovisual error. At certain threshold being set on this psychovisual error, the new quantization table can be generated. The experimental results show that the new quantization table from psychovisual error threshold for DCT basis functions gives better quality image at lower average bit length of Huffman code than standard JPEG image compression.