Y
Yury Audzevich
Researcher at University of Cambridge
Publications - 17
Citations - 965
Yury Audzevich is an academic researcher from University of Cambridge. The author has contributed to research in topics: Network packet & NetFPGA. The author has an hindex of 8, co-authored 17 publications receiving 828 citations. Previous affiliations of Yury Audzevich include University of Trento.
Papers
More filters
Proceedings ArticleDOI
GreenCloud: A Packet-Level Simulator of Energy-Aware Cloud Computing Data Centers
TL;DR: The simulation results obtained for two-tier, three- tier, and three-tier high-speed data center architectures demonstrate the effectiveness of the simulator in utilizing power management schema, such as voltage scaling, frequency scaling, and dynamic shutdown that are applied to the computing and networking components.
Journal ArticleDOI
NetFPGA SUME: Toward 100 Gbps as Research Commodity
TL;DR: NetFPGA SUME is an FPGA-based PCI Express board with I/O capabilities for 100 Gbps operation as a network interface card, multiport switch, firewall, or test and measurement environment.
Proceedings ArticleDOI
Understanding PCIe performance for end host networking
Rolf Neugebauer,Gianni Antichi,Jose Fernando Zazo,Yury Audzevich,Sergio Lopez-Buedo,Andrew W. Moore +5 more
TL;DR: A theoretical model for PCIe and pcie-bench, an open-source suite, are presented that allows developers to gain an accurate and deep understanding of the PCIe substrate, and insights are gained which guided software and future hardware architectures for both commercial and research oriented network cards and DMA engines.
Proceedings ArticleDOI
NetFPGA: Rapid Prototyping of Networking Devices in Open Source
Noa Zilberman,Yury Audzevich,Georgina Kalogeridou,Neelakandan Manihatty-Bojan,Jingyun Zhang,Andrew W. Moore +5 more
TL;DR: NetFPGA is demonstrated, an open-source platform for rapid prototyping of networking devices with I/O capabilities up to 100Gbps that offers an integrated environment that enables networking research by users from a wide range of disciplines: from hardware-centric research to formal methods.
Proceedings ArticleDOI
A PCIe DMA engine to support the virtualization of 40 Gbps FPGA-accelerated network appliances
TL;DR: A PCIe DMA engine that allows boosting the performance of virtual network appliances by using FPGA accelerators, and is a very compact design, using just 2% of a Xilinx Virtex-7 XC7VX690T device.