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Yutaka Nakamura

Researcher at IBM

Publications -  27
Citations -  5189

Yutaka Nakamura is an academic researcher from IBM. The author has contributed to research in topics: Sense amplifier & Logic gate. The author has an hindex of 11, co-authored 27 publications receiving 3953 citations.

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Journal ArticleDOI

A million spiking-neuron integrated circuit with a scalable communication network and interface

TL;DR: Inspired by the brain’s structure, an efficient, scalable, and flexible non–von Neumann architecture is developed that leverages contemporary silicon technology and is well suited to many applications that use complex neural networks in real time, for example, multiobject detection and classification.
Journal ArticleDOI

TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip

TL;DR: This work developed TrueNorth, a 65 mW real-time neurosynaptic processor that implements a non-von Neumann, low-power, highly-parallel, scalable, and defect-tolerant architecture, and successfully demonstrated the use of TrueNorth-based systems in multiple applications, including visual object recognition.
Journal ArticleDOI

An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches

TL;DR: An eight-transistor (8T) cell can be designed without significant area penalty over 6T-SRAM while providing substantially improved variability tolerance and low-voltage operation with no need for secondary or dynamic power supplies.
Proceedings ArticleDOI

A 5.3GHz 8T-SRAM with Operation Down to 0.41V in 65nm CMOS

TL;DR: In this article, a 32-kb subarray is implemented with a 65 nm node 8T-SRAM cell for variability tolerance in high-speed caches, achieving 5.3 GHz operation at 1.2 V.