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Yutaka Nakamura
Researcher at IBM
Publications - 27
Citations - 5189
Yutaka Nakamura is an academic researcher from IBM. The author has contributed to research in topics: Sense amplifier & Logic gate. The author has an hindex of 11, co-authored 27 publications receiving 3953 citations.
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Journal ArticleDOI
A million spiking-neuron integrated circuit with a scalable communication network and interface
Paul A. Merolla,John V. Arthur,Rodrigo Alvarez-Icaza,Andrew S. Cassidy,Jun Sawada,Filipp Akopyan,Bryan L. Jackson,Nabil Imam,Chen Guo,Yutaka Nakamura,Bernard Brezzo,Ivan Vo,Steven K. Esser,Rathinakumar Appuswamy,Brian Taba,Arnon Amir,Myron D. Flickner,William P. Risk,Rajit Manohar,Dharmendra S. Modha +19 more
TL;DR: Inspired by the brain’s structure, an efficient, scalable, and flexible non–von Neumann architecture is developed that leverages contemporary silicon technology and is well suited to many applications that use complex neural networks in real time, for example, multiobject detection and classification.
Journal ArticleDOI
TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip
Filipp Akopyan,Jun Sawada,Andrew S. Cassidy,Rodrigo Alvarez-Icaza,John V. Arthur,Paul A. Merolla,Nabil Imam,Yutaka Nakamura,Pallab Datta,Gi-Joon Nam,Brian Taba,Michael P. Beakes,Bernard Brezzo,Jente B. Kuang,Rajit Manohar,William P. Risk,Bryan L. Jackson,Dharmendra S. Modha +17 more
TL;DR: This work developed TrueNorth, a 65 mW real-time neurosynaptic processor that implements a non-von Neumann, low-power, highly-parallel, scalable, and defect-tolerant architecture, and successfully demonstrated the use of TrueNorth-based systems in multiple applications, including visual object recognition.
Journal ArticleDOI
An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches
Leland Chang,Robert K. Montoye,Yutaka Nakamura,Kevin A. Batson,Richard J. Eickemeyer,Robert H. Dennard,Wilfried Haensch,Damir Jamsek +7 more
TL;DR: An eight-transistor (8T) cell can be designed without significant area penalty over 6T-SRAM while providing substantially improved variability tolerance and low-voltage operation with no need for secondary or dynamic power supplies.
Proceedings ArticleDOI
A 5.3GHz 8T-SRAM with Operation Down to 0.41V in 65nm CMOS
Leland Chang,Yutaka Nakamura,R. K. Montoye,Jun Sawada,Andrew K. Martin,K. Kinoshita,Fadi H. Gebara,Kanak B. Agarwal,Dhruva Acharyya,Wilfried Haensch,Kohji Hosokawa,Damir A. Jamsek +11 more
TL;DR: In this article, a 32-kb subarray is implemented with a 65 nm node 8T-SRAM cell for variability tolerance in high-speed caches, achieving 5.3 GHz operation at 1.2 V.
Proceedings ArticleDOI
Real-time scalable cortical computing at 46 giga-synaptic OPS/watt with ~100× speedup in time-to-solution and ~100,000× reduction in energy-to-solution
Andrew S. Cassidy,Rodrigo Alvarez-Icaza,Filipp Akopyan,Jun Sawada,John V. Arthur,Paul A. Merolla,Pallab Datta,Marc Gonzalez Tallada,Brian Taba,Alexander Andreopoulos,Arnon Amir,Steven K. Esser,Jeff Kusnitz,Rathinakumar Appuswamy,C. Haymes,Bernard Brezzo,Roger Moussalli,Ralph Bellofatto,Christian W. Baks,Michael Mastro,Kai Schleupen,Charles Edwin Cox,Ken Inoue,Steve Millman,Nabil Imam,Emmett McQuinn,Yutaka Nakamura,Ivan Vo,Chen Guok,Don Nguyen,Scott Lekuch,Sameh W. Asaad,Daniel Friedman,Bryan L. Jackson,Myron D. Flickner,William P. Risk,Rajit Manohar,Dharmendra S. Modha +37 more
TL;DR: True North is a 4,096 core, 1 million neuron, and 256 million synapse brain-inspired neurosynaptic processor, that consumes 65mW of power running at real-time and delivers performance of 46 Giga-Synaptic OPS/Watt.