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Yvonne Y. H. Lam

Bio: Yvonne Y. H. Lam is an academic researcher from Nanyang Technological University. The author has contributed to research in topics: Successive approximation ADC & Iterative reconstruction. The author has an hindex of 7, co-authored 20 publications receiving 246 citations.

Papers
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Journal ArticleDOI
TL;DR: In this article, a tri-level switching scheme for low-power successive approximation register (SAR) ADC is proposed, which reduces the number of capacitors in the ADC capacitor array by 75% and results in an area-efficient SAR ADC.
Abstract: A novel low-energy tri-level switching scheme for low-power successive approximation register (SAR) ADC is proposed. With the input common-mode voltage ( Vcm ) designed to be exactly half of the reference voltage ( Vref ), the switching energy of the proposed switching scheme is reduced by 96.89% as compared with the conventional architecture. Besides the large energy saving, the proposed switching scheme also reduces the number of capacitors in the ADC capacitor array by 75%, which in turn results in an area-efficient SAR ADC.

160 citations

Proceedings ArticleDOI
23 Sep 2011
TL;DR: In this paper, a novel ultra low-power rail-to-rail comparator is presented, which can be suitably used in low to medium speed A/D converters.
Abstract: This paper presents a novel ultra low-power rail-to-rail comparator which can be suitably used in low-to-medium speed A/D converters. This comparator adopts a preamplifier followed by a dynamic latch structure to achieve fast-decision, high-resolution as well as reduced kick-back noise. A new adaptive power control technique is used to reduce the power consumption of the preamplifier. The circuit is designed and simulated in Global Foundries 65nm CMOS technology. The simulation results have shown that the power consumption of 12-bit comparator is 191.2 nW at the clock frequency of 15 MHz and 0.8 V supply voltage with a delay of 1.17nS.

21 citations

Proceedings ArticleDOI
19 May 2013
TL;DR: This paper describes a low-kS/s successive approximation register (SAR) analog-to-digital converter (ADC) for biomedical applications that employs a novel low-energy and area-efficient tri-level switching scheme in the DAC.
Abstract: This paper describes a low-power 25-kS/s successive approximation register (SAR) analog-to-digital converter (ADC) for biomedical applications. The ADC employs a novel low-energy and area-efficient tri-level switching scheme in the DAC. Compared to the conventional SAR ADC, the average switching energy and total capacitance are reduced by 97% and 75%, respectively. Asynchronous design is implemented to eliminate the conventional system clock which is N-time of sampling rate. Furthermore, a delay-based internal clock generator produces a high-speed signal which allows True Single Phase Clock (TSPC) D Flip-flop (DFF) to be used in the low-speed biomedical applications. The ADC can work between 0 to 1 MS/s. The prototype ADC fabricated in UMC 65 nm 1P6M CMOS achieves best performance at 25 kS/s with 50.1 dB SNDR and 55.3 dB SFDR. Operating at 1 V supply and 25 kS/s, the ADC consumes 281 nW and exhibits a FOM of 43.3 fJ/conversion-step. The chip die area is 145 μm × 120 μm.

19 citations

Journal ArticleDOI
TL;DR: Simulations using real phantom data demonstrate that the proposed cascaded reconstruction beamformer that uses a boxcar filter as the pre-delay filter in each channel can achieve a contrast resolution comparable to that of thePre-delay reconstruction beamforming method.
Abstract: A pre-delay reconstruction sigma-delta beamformer (SDBF) was recently proposed to achieve a higher level of integration in ultrasound imaging systems. Nevertheless, the high-order reconstruction filter used in each channel of SDBF makes the beamformer highly complex. The beamformer can be simplified by reconstructing the signal after the delay-andsum process with only one filter. However, this post-delay reconstruction-based design degrades image quality when dynamic focusing is performed. This paper shows that employing a simple pre-delay filter is sufficient to achieve similar performance as conventional pre-delay reconstruction SDBF, as long as the pre-delay filter provides the required pre-delay signalto- quantization noise ratio (SQNR). Based on this finding, we proposed a cascaded reconstruction beamformer that uses a boxcar filter as the pre-delay filter in each channel. Simulations using real phantom data demonstrate that the proposed beamforming method can achieve a contrast resolution comparable to that of the pre-delay reconstruction beamforming method. In addition, the hardware can be greatly simplified compared with the pre-delay reconstruction beamformers.

14 citations

Proceedings ArticleDOI
01 Aug 2007
TL;DR: In this article, a low power high speed continuous-time (CT) delta-sigma modulator (DSM) for ultrasound application is presented, which can achieve a dynamic range of 61.5 dB and consume only 3.4 mW power at 1.8 V supply voltage.
Abstract: This paper presents a low power high speed continuous-time (CT) delta-sigma modulator (DSM) for ultrasound application. The modulator was designed for a portable ultrasound digital beamformer to digitize ultrasound signal centered at 3.5 MHz with a fractional bandwidth of 0.6. A CMOS 0.18 mum 3rd-order low-pass DSM sampled at 200 MHz was implemented. A transconductor (Gm) with improved linearity was proposed in order to reduce the power dissipation by increasing its linear input range. Simulation shows that the DSM can achieve a dynamic range of 61.5 dB and consume only 3.4 mW power at 1.8 V supply voltage.

11 citations


Cited by
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Journal ArticleDOI
TL;DR: In this article, a novel energy-efficient V676 CM-based monotonic capacitor switching scheme for successive approximation register (SAR) analogue to-digital converters (ADCs) is proposed.
Abstract: A novel energy-efficient V CM -based monotonic capacitor switching scheme for successive approximation register (SAR) analogue to-digital converters (ADCs) is proposed. Based on the third reference voltage V CM and monotonic capacitor switching procedure, the proposed switching scheme achieves 97.66% less switching energy and 75% less number of capacitors over the conventional architecture, resulting in the most energy-efficient switching scheme among the reported switching sequences.

133 citations

Journal ArticleDOI
TL;DR: A high energy-efficiency switching scheme for a successive approximation register (SAR) analogue-to-digital converter (ADC) is presented and can achieve 98.4% savings in switching energy when compared to a conventional SAR.
Abstract: A high energy-efficiency switching scheme for a successive approximation register (SAR) analogue-to-digital converter (ADC) is presented. The proposed method can achieve 98.4% savings in switching energy when compared to a conventional SAR. The proposed technique also achieves a 4 % reduction in total capacitance used in the digital-to-analogue converter (DAC) compared to the conventional DAC.

106 citations

Journal ArticleDOI
TL;DR: An improved comparator with push-pull pre-amplifier and output offset storage (OOS) strategy is proposed to diminish non-linearity in the input parasitic capacitance to reduce the power consumption and the matching requirement for capacitors in SAR ADCs.
Abstract: A 12-bit 10 MS/s SAR ADC with enhanced linearity and energy efficiency is presented in this paper. A novel switching scheme (COSS) is proposed to reduce the power consumption and the matching requirement for capacitors in SAR ADCs. The switching energy (including switching energy and reset energy), total capacitance and static performance (INL & DNL) of the proposed scheme are reduced by 98.08%, 75%, and 75%, respectively, compared with the conventional architecture. Based on analysis of the non-linear errors caused by comparator input parasitic capacitance, an improved comparator with push-pull pre-amplifier and output offset storage (OOS) strategy is proposed to diminish non-linearity in the input parasitic capacitance. The offset cancellation signal for the comparator can be generated by asynchronous timing automatically, without any extra clock. Additionally, an SFDR enhancement bootstrap switch is proposed to eliminate the distortion induced by parasitic capacitance and threshold voltage that results in insufficient precision for medium-speed 12-bit ADCs. The proposed ADC was fabricated in a 0.18 $\mu\text{m}$ 1P6M CMOS process, and the measured results show that the ADC achieves an SNDR of 66.9 dB and an SFDR of 75.8 dB with a 10 MS/s sampling rate and consumes 0.82 mW, resulting in a figure of merit (FOM) of 44.2 fJ/conversion-step. The peak DNL error is +0.36/−0.33 LSB, and the peak INL error is +0.55 LSB/−0.6 LSB. The ADC core occupies an active area of only $630\ \mu\text{m}\! \times\! 570\ \mu\text{m}^{2}$ .

94 citations

Journal ArticleDOI
TL;DR: A pixel pitch-matched readout chip for 3-D photoacoustic (PA) imaging, featuring a dedicated signal conditioning and delta-sigma modulation integrated within a pixel area of 250, that obviates the need for area-consuming Nyquist ADCs and enables an efficient in-pixel A/D conversion.
Abstract: This paper presents a pixel pitch-matched readout chip for 3-D photoacoustic (PA) imaging, featuring a dedicated signal conditioning and delta-sigma modulation integrated within a pixel area of 250 $\mu \text{m}$ by 250 $\mu \text{m}$ . The proof-of-concept receiver was implemented in an STMicroelectronics’s 28-nm Fully Depleted Silicon On Insulator technology, and interfaces to a $4 \times 4$ subarray of capacitive micromachined ultrasound transducers (CMUTs). The front-end signal conditioning in each pixel employs a coarse/fine gain tuning architecture to fulfill the 90-dB dynamic range requirement of the application. The employed delta-sigma beamforming architecture obviates the need for area-consuming Nyquist ADCs and thereby enables an efficient in-pixel A/D conversion. The per-pixel switched-capacitor $\Delta \Sigma $ modulator leverages slewing-dominated and area-optimized inverter-based amplifiers. It occupies only 1/4th of the pixel, and its area compares favorably with state-of-the-art designs that offer the same SNR and bandwidth. The modulator’s measured peak signal-to-noise-and-distortion ratio is 59.9 dB for a 10-MHz input bandwidth, and it consumes 6.65 mW from a 1-V supply. The overall subarray beamforming approach improves the area per channel by 7.4 times and the single-channel SNR by 8 dB compared to prior art with similar delay resolution and power dissipation. The functionality of the designed chip was evaluated within a PA imaging experiment, employing a flip-chip bonded 2-D CMUT array.

88 citations

Journal ArticleDOI
TL;DR: In this paper, a low-energy hybrid capacitor switching scheme for a low power successive approximation register (SAR) analogue-to-digital converter (ADC) is presented, which combines a new switch method and the monotonic technique.
Abstract: A novel low-energy hybrid capacitor switching scheme for a low-power successive approximation register (SAR) analogue-to-digital converter (ADC) is presented. The proposed switching scheme combines a new switch method and the monotonic technique. The new switch method can achieve no switching energy consumption in the first three comparison cycles. Furthermore, a low-energy monotonic procedure is performed for the rest of the comparisons. The average switching energy is reduced by 98.83% compared with the conventional architecture, resulting in the most energy-efficient switching scheme among the existing switching techniques. Besides the significant energy saving, the proposed switching scheme also achieves a 75% reduction of the capacitors over the conventional scheme.

74 citations