Author
Zainalabedin Navabi
Other affiliations: Payame Noor University, Northeastern University, University College of Engineering ...read more
Bio: Zainalabedin Navabi is an academic researcher from University of Tehran. The author has contributed to research in topics: Fault coverage & Hardware description language. The author has an hindex of 23, co-authored 274 publications receiving 2262 citations. Previous affiliations of Zainalabedin Navabi include Payame Noor University & Northeastern University.
Papers published on a yearly basis
Papers
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01 Dec 1997
TL;DR: The new second edition of the authoritative reference engineers need to guide them through the use of VHDL hardware description language in the analysis, simulation, and modeling of complicated microelectronic circuits is released, including new chapters on design flow, interfacing, modeling, and timing.
Abstract: From the Publisher:
Here's the new second edition of the authoritative reference engineers need to guide them through the use of VHDL hardware description language in the analysis, simulation, and modeling of complicated microelectronic circuits. You'll find extensive new material to bring the guide fully up to date with the new VHDL93 standard, including new chapters on design flow, interfacing, modeling, and timing. Extensive appendixes, including ones on logic synthesis and CPU description styles, provide up-to-date information on the use of VHDL in design. The number and depth of its relevant and practical examples and problems is what sets this edition apart from other VHDL texts.
314 citations
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TL;DR: The simulation results reveal that EDXY can achieve lower latency compared to those of other adaptive routing algorithms across all workloads examined, with a 20% average and 30% maximum latency reduction on SPLASH-2 benchmarks running on a 49-core CMP.
86 citations
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13 Dec 2005TL;DR: A pseudo adaptive routing which is an extension of classic XY routing is proposed, which has two deterministic and adaptive modes that status of neighbors of each switch is used to decide on which mode must be selected.
Abstract: In this paper we propose a pseudo adaptive routing which is an extension of classic XY routing We consider mesh topology for evaluating proposed routing Our switches use pseudo adaptive XY routing algorithm The load in the center of a network in ordinary XY routing is much higher rather than total average This extra load on the center of mesh can cause spot hot The main objective of our routing algorithm is to distribute network load One of the advantages of distributing network load is balanced temperature on the mesh Our routing algorithm has two deterministic and adaptive modes that status of neighbors of each switch is used to decide on which mode must be selected Packets are routed with classic XY routing (deterministic mode), when congestion in the network is low When congestion is high, packets are routed through less congested route adaptively (adaptive mode) We developed a NOC environment using SystemC and applied two multimedia applications and a random traffic to proposed routing and compared with classic XY routing Experimental results show better latency while average load is unchanged
85 citations
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10 Dec 2010
TL;DR: Describing many of the on-chip decompression algorithms in Verilog helps to evaluate these algorithms in terms of hardware overhead and timing, and thus feasibility of using them for System-on-Chip designs.
Abstract: This book is about digital system testing and testable design. The concepts of testing and testability are treated together with digital design practices and methodologies. The book uses Verilog models and testbenches for implementing and explaining fault simulation and test generation algorithms. Extensive use of Verilog and Verilog PLI for test applications is what distinguishes this book from other test and testability books. Verilog eliminates ambiguities in test algorithms and BIST and DFT hardware architectures, and it clearly describes the architecture of the testability hardware and its test sessions. Describing many of the on-chip decompression algorithms in Verilog helps to evaluate these algorithms in terms of hardware overhead and timing, and thus feasibility of using them for System-on-Chip designs. Extensive use of testbenches and testbench development techniques is another unique feature of this book. Using PLI in developing testbenches and virtual testers provides a powerful programming tool, interfaced with hardware described in Verilog. This mixed hardware/software environment facilitates description of complex test programs and test strategies.
81 citations
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26 Sep 2007TL;DR: A high level fault model has been proposed in this paper to model switch routing faults and the proposed method is evaluated by fault simulation that is based on the high-level fault model.
Abstract: This paper presents an efficient method for online testing of NoC switches. This method deals with control faults of NoC switches; i.e. the routing faults which cause NoC packets to be sent to output ports not intended to. A high level fault model has been proposed in this paper to model switch routing faults. The proposed method is evaluated by fault simulation that is based on our high-level fault model. This simulation and evaluation environment is modeled at the transaction level in VHDL.
79 citations
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TL;DR: “Spintronics,” in which both the spin and charge of electrons are used for logic and memory operations, promises an alternate route to traditional semiconductor electronics.
Abstract: “Spintronics,” in which both the spin and charge of electrons are used for logic and memory operations, promises an alternate route to traditional semiconductor electronics. A complete logic architecture can be constructed, which uses planar magnetic wires that are less than a micrometer in width. Logical NOT, logical AND, signal fan-out, and signal cross-over elements each have a simple geometric design, and they can be integrated together into one circuit. An additional element for data input allows information to be written to domain-wall logic circuits.
1,955 citations
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29 Jan 2003TL;DR: It is argued that modeling systems in this manner leads to unexpected and hard-to-analyze interactions between the communication mechanisms and proposes a more structured approach to heterogeneity, called hierarchical heterogeneity, to solve this problem.
Abstract: Modern embedded computing systems tend to be heterogeneous in the sense of being composed of subsystems with very different characteristics, which communicate and interact in a variety of ways-synchronous or asynchronous, buffered or unbuffered, etc. Obviously, when designing such systems, a modeling language needs to reflect this heterogeneity. Today's modeling environments usually offer a variant of what we call amorphous heterogeneity to address this problem. This paper argues that modeling systems in this manner leads to unexpected and hard-to-analyze interactions between the communication mechanisms and proposes a more structured approach to heterogeneity, called hierarchical heterogeneity, to solve this problem. It proposes a model structure and semantic framework that support this form of heterogeneity, and discusses the issues arising from heterogeneous component interaction and the desire for component reuse. It introduces the notion of domain polymorphism as a way to address these issues.
1,146 citations
01 Nov 1997
TL;DR: Recognizing the mannerism ways to get this books computer organization and design the hardware software interface 4th fourth edition by patterson hennessy is additionally useful.
Abstract: Recognizing the mannerism ways to get this books computer organization and design the hardware software interface 4th fourth edition by patterson hennessy is additionally useful. You have remained in right site to begin getting this info. acquire the computer organization and design the hardware software interface 4th fourth edition by patterson hennessy join that we manage to pay for here and check out the link.
832 citations
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TL;DR: This paper provides a general description of NoC architectures and applications and enumerates several related research problems organized under five main categories: Application characterization, communication paradigm, communication infrastructure, analysis, and solution evaluation.
Abstract: To alleviate the complex communication problems that arise as the number of on-chip components increases, network-on-chip (NoC) architectures have been recently proposed to replace global interconnects. In this paper, we first provide a general description of NoC architectures and applications. Then, we enumerate several related research problems organized under five main categories: Application characterization, communication paradigm, communication infrastructure, analysis, and solution evaluation. Motivation, problem description, proposed approaches, and open issues are discussed for each problem from system, microarchitecture, and circuit perspectives. Finally, we address the interactions among these research problems and put the NoC design process into perspective.
733 citations
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TL;DR: This book is mainly oriented towards a final year undergraduate course on fault-tolerant computing, primarily with an implementation bias, and draws considerably on the author's experience in industry, particularly reflected in the projects accompanying chapter 5.
Abstract: Design and Analysis ofFault-Tolerant Digital Systems: B. W. JOHNSON (Addison Wesley, 1989,577 pp., £41.35) The book provides an introduction to the important aspects of designing fault-tolerant systems, and an evaluation of how well the reliability goals have been achieved. The book is mainly oriented towards a final year undergraduate course on fault-tolerant computing, primarily with an implementation bias. In chapters 1 and 2, definitions and basic terminology are covered, which sets the stage for the remaining chapters, and provides the background and motivation for the remainder of the book. Chapter 3 provides a thorough analysis of fault-tolerance techniques and concepts. This chapter in particular is remarkably well written, covering the issues of hardware and information redundancy, which form the mainstay offault-tolerant computing. Subsequent chapters on the use and evaluation of the various approaches illustrate the principles as they have been put into practice. At the end of chapter 5, small projects that allow the reader to apply the material presented in the preceding chapters are included. The resurgence of interest in fault-tolerance with the emergence of VLSI is the theme of chapter 6, focussing on designing fault-tolerant systems in a VLSI environment. The problems and opportunities presented by VLSI are discussed and the use of redundancy techniques in order to enhance manufacturing yield and to provide in-service reliability are reviewed. The final chapter covers testing, design for testability and testability analysis, which must be considered during each phase of the design process to guarantee that resulting designs can be thoroughly tested. Each chapter is followed by a summary of the key issues and concepts presented therein, and a separate list of references, which makes it easily readable. In addition, there is a reading list with more comprehensive and specialised references devoted to each chapter. Overall, the book is well written, and contains a great deal of information in 577 pages. The book has a definite implementation bias, and draws considerably on the author's experience in industry, particularly reflected in the projects accompanying chapter 5. The book should be a useful addition to a library, and a suitable text to accompany a lecture course on fault-tolerant computing. R. RAMASWAMI, Department ofComputation, UMIST
444 citations