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Zhangming Zhu

Bio: Zhangming Zhu is an academic researcher from Xidian University. The author has contributed to research in topics: Successive approximation ADC & CMOS. The author has an hindex of 22, co-authored 334 publications receiving 2462 citations. Previous affiliations of Zhangming Zhu include Chinese Academy of Sciences & Yunnan University.


Papers
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Journal ArticleDOI
TL;DR: In this article, a novel energy-efficient V676 CM-based monotonic capacitor switching scheme for successive approximation register (SAR) analogue to-digital converters (ADCs) is proposed.
Abstract: A novel energy-efficient V CM -based monotonic capacitor switching scheme for successive approximation register (SAR) analogue to-digital converters (ADCs) is proposed. Based on the third reference voltage V CM and monotonic capacitor switching procedure, the proposed switching scheme achieves 97.66% less switching energy and 75% less number of capacitors over the conventional architecture, resulting in the most energy-efficient switching scheme among the reported switching sequences.

133 citations

Journal ArticleDOI
TL;DR: An improved comparator with push-pull pre-amplifier and output offset storage (OOS) strategy is proposed to diminish non-linearity in the input parasitic capacitance to reduce the power consumption and the matching requirement for capacitors in SAR ADCs.
Abstract: A 12-bit 10 MS/s SAR ADC with enhanced linearity and energy efficiency is presented in this paper. A novel switching scheme (COSS) is proposed to reduce the power consumption and the matching requirement for capacitors in SAR ADCs. The switching energy (including switching energy and reset energy), total capacitance and static performance (INL & DNL) of the proposed scheme are reduced by 98.08%, 75%, and 75%, respectively, compared with the conventional architecture. Based on analysis of the non-linear errors caused by comparator input parasitic capacitance, an improved comparator with push-pull pre-amplifier and output offset storage (OOS) strategy is proposed to diminish non-linearity in the input parasitic capacitance. The offset cancellation signal for the comparator can be generated by asynchronous timing automatically, without any extra clock. Additionally, an SFDR enhancement bootstrap switch is proposed to eliminate the distortion induced by parasitic capacitance and threshold voltage that results in insufficient precision for medium-speed 12-bit ADCs. The proposed ADC was fabricated in a 0.18 $\mu\text{m}$ 1P6M CMOS process, and the measured results show that the ADC achieves an SNDR of 66.9 dB and an SFDR of 75.8 dB with a 10 MS/s sampling rate and consumes 0.82 mW, resulting in a figure of merit (FOM) of 44.2 fJ/conversion-step. The peak DNL error is +0.36/−0.33 LSB, and the peak INL error is +0.55 LSB/−0.6 LSB. The ADC core occupies an active area of only $630\ \mu\text{m}\! \times\! 570\ \mu\text{m}^{2}$ .

94 citations

Journal ArticleDOI
TL;DR: A novel switching scheme is proposed, which can accomplish the first three comparisons without consuming any energy and thus improve the energy efficiency significantly, and boost the offset performance of the comparator working under low supply voltage.
Abstract: This paper presents a 10-bit ultra-low power successive approximation register (SAR) analog-to-digital converter (ADC) for implantable medical devices. To achieve the nanowatt range power consumption, a novel switching scheme is proposed, which can accomplish the first three comparisons without consuming any energy and thus improve the energy efficiency significantly. In addition, to boost the offset performance of the comparator working under low supply voltage, a detailed theoretical analysis of comparator offset voltages is made. Based on the analysis, the comparator is optimized by only adjusting transistor sizes without any particular offset cancellation. As a result, when the common-mode input voltage varies from 300 mV to 450 mV at a 0.6 V supply, the $3\times\sigma$ offset voltage is optimized to be about 6 mV with a fluctuation of only 0.15 mV, as revealed by Monte Carlo simulations. A prototype of the proposed ADC was fabricated in 0.18 $\mu{\rm m}$ 1P6M CMOS technology, which occupies an active area of only $380\times 430\ \mu{\rm m}^{2}$ . At a 0.6-V supply and 20 kS/s sampling rate, the ADC achieves an SNDR of 58.3 dB and a power consumption of 38 nW, resulting in a figure of merit (FOM) of 2.8 fJ/conversion-step.

89 citations

Journal ArticleDOI
TL;DR: By employing a bulk-driven technique and the MOS transistors working in the subthreshold region, the supply voltage and the power dissipation are reduced and a trimming circuit is adopted to compensate for the process-related reference voltage variation.
Abstract: We present a low-voltage low-power CMOS subthreshold voltage reference with no resistors and no bipolar junction transistors in a wide temperature range. The temperature stability is improved by second-order compensation. By employing a bulk-driven technique and the MOS transistors working in the subthreshold region, the supply voltage and the power dissipation are reduced. Moreover, a trimming circuit is adopted to compensate for the process-related reference voltage variation. The proposed voltage reference has been fabricated with the 0.18- $\mu\text{m} $ 1.8-V CMOS process. The measurement results show that the minimum power supply voltage is 0.45 V, the power consumption is 14.6 nW, the average temperature coefficient measured from $-40\ ^{\circ}\mbox{C} $ to 125 °C is 63.6 ppm/°C, and the line regulation is 1.2 mV/V in the power supply voltage ranging from 0.45 to 1.8 V. In addition, the chip area is 0.012 mm2.

85 citations

Journal ArticleDOI
TL;DR: An asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) for sensor applications is presented and high linear and power efficient switching scheme is proposed.
Abstract: An asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) for sensor applications is presented. High linear and power efficient switching scheme is proposed. The proposed low leakage latched dynamic cell in SAR logic and wide range configurable delay element extend the flexibility of speed and resolution tradeoff. The ADC fabricated in 0.18 μm CMOS process covers 6-10 bit resolution and 0.5 V-0.9 V power supply range. At 10 bit mode and 0.5 V operation, the proposed SAR ADC achieves 56.36 dB SNDR and 67.96 dB SFDR with sampling rate up to 2 MS/s, corresponding to a figure-of-merit of 20.6 fJ/conversion-step. The proposed ADC core occupies an active area of about 300×700 μm 2 .

72 citations


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Journal ArticleDOI

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Abstract: There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality. Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

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TL;DR: It is suggested that the natural selection against large insertion/deletion is so weak that a large amount of variation is maintained in a population.

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01 Jan 2016
TL;DR: The design of analog cmos integrated circuits is universally compatible with any devices to read and is available in the book collection an online access to it is set as public so you can download it instantly.
Abstract: Thank you for downloading design of analog cmos integrated circuits. Maybe you have knowledge that, people have look hundreds times for their chosen books like this design of analog cmos integrated circuits, but end up in malicious downloads. Rather than enjoying a good book with a cup of coffee in the afternoon, instead they juggled with some harmful virus inside their computer. design of analog cmos integrated circuits is available in our book collection an online access to it is set as public so you can download it instantly. Our digital library spans in multiple countries, allowing you to get the most less latency time to download any of our books like this one. Kindly say, the design of analog cmos integrated circuits is universally compatible with any devices to read.

1,038 citations

01 Jan 2016
TL;DR: The design of analog cmos integrated circuits is universally compatible with any devices to read and is available in the book collection an online access to it is set as public so you can download it instantly.
Abstract: Thank you very much for downloading design of analog cmos integrated circuits. Maybe you have knowledge that, people have look hundreds times for their favorite novels like this design of analog cmos integrated circuits, but end up in malicious downloads. Rather than reading a good book with a cup of coffee in the afternoon, instead they cope with some malicious virus inside their laptop. design of analog cmos integrated circuits is available in our book collection an online access to it is set as public so you can download it instantly. Our digital library saves in multiple countries, allowing you to get the most less latency time to download any of our books like this one. Merely said, the design of analog cmos integrated circuits is universally compatible with any devices to read.

912 citations

Journal ArticleDOI
01 Dec 2008

636 citations