This paper presents a method of tuning the gate length and width in a standard cell for reuse, which includes the algorithm for auto-identification, obtaining of the gate information and tuning of the locations and/or sizes of the related layout patterns. Existing layouts of standard cells are reused to design new standard cells. Experimental results show that this method can improve the efficiency of standard cell designs and facilitate the generation of standard cells satisfying the requirements of physical optimization.

A method of automatically tuning gate length and width in a standard cell

Due to the unbalance between the development of EDA system and IC process technique,the layout reuse technique is demanded on the market.The existing layout should be compacted to fit for the new process technique. An efficient 2\|D compaction algorithm is proposed,which is based on the constraint graph expression of the figures on layout and newly designed rules.In order to do compaction on the chip level, a hierarchical strategy and the ‘fall leaves pool’ data structure are used,regarding the interconnections as soft lines it also can add to jogs automatically.From the test cases it is shown that this compaction algorithm is practical and effective.

Zhao Zi

Papers

2-D Hierarchical Compaction Algorithm for VLSI Layout Reuse