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Author

Zhengwu Yu

University of Science and Technology of China
Bio: Zhengwu Yu is an academic researcher from University of Science and Technology of China. The author has contributed to research in topics: Control theory. The author has co-authored 1 publications.
Topics: Control theory
Papers
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Proceedings Article•DOI•
TMS320C25 module with a dual-bank data memory under PC-bus

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Zhengwu Yu1, Jingcheng Wang1, Lansun Shen1•
University of Science and Technology of China1
16 Jun 1991
TL;DR: The authors discuss a dual- bank controller with GAL chips, present a TMS320C25 module with the dual-bank data memory under PC-bus, and describe the module's features.
Abstract: With the shortage of facilities for general control, TMS320C25 is often used as the slave processor in a master-slave system. The authors introduce the concepts and relationships of various common memories (like dual-access, dual-port and dual-bank memory), through which communication between any two processors can take place. Accordingly, the authors discuss a dual-bank controller with GAL chips, present a TMS320C25 module with the dual-bank data memory under PC-bus, and describe the module's features. >