Zhenrui Zhang

Bio: Zhenrui Zhang is an academic researcher from Chinese Academy of Sciences. The author has contributed to research in topics: System on a chip & Logic gate. The author has an hindex of 2, co-authored 2 publications receiving 6 citations.

Video image motion compensator

Abstract: The invention consists of motion vector prediction module, pixel data readout module and pixel interplation module. The motion vector prediction module figures out the motion vector of macro block according to residual error of motion vector in bitstream and standard algorithm. The motion vector of macro block is transmitted to the pixel data readout module via first buffer module. The pixel data readout module receives the read back data from external storage according to address of external storage. The data is made splicing and un-limiting motion vector process, and is transmitted to pixel interplation module via second buffer module. The pixel interplation module takes standard interplation algorithm.

A flexible VLSI architecture of transport processor for an AVS HDTV decoder SoC

Abstract: In this paper, we present a VLSI design of transport processor for an AVS HDTV decoder SoC. The design provides a flexible data flow, which supports both broadcasting service and IPTV service with DVR capability. The design is characterized by two-bus architecture, in which a RISC CPU is used for control of general purpose and some dedicated hardware for accelerating data processing. The common on-chip SRAM is used to store input transport packets and the intermediate result in order to improve system performance and reduce the area. The design is described in Verilog HDL, simulated with VCS simulator, and implemented using 0.18 mum CMOS cell library. The circuit costs about 75 k equivalent logic gates and the processing capability is up to 90 Mbps

A 5Mgate/414mW networked media SoC in 0.13um CMOS with 720p multi-standard video decoding

Abstract: A flexible and high performance SoC is developed for networked media applications by integrating two RISC cores, Ethernet interface and coarse-grained configurable video decoding unit. Real-time 1280×720@25fps MPEG-2/MPEG-4/RealVideo decoding is achieved for on-line video streams. The SoC is fabricated in 0.13um single-poly eight-metal CMOS technology with die size of 6.4mm × 6.4mm. To achieve low power design, flexible power management strategy is implemented including dynamic configuration of clock frequency synthesis and module level clock gating according to the workloads. The maximum power consumption is 414mW at 1.2V supply voltage with the corresponding system frequency of 216MHz, when real-time HD (1280×720@25fps) video streams are decoded. The power consumption is reduced to 95mW for real-time CIF (352×288@25fps) video stream decoding at 27MHz system frequency.

A high performance advanced encryption standard (AES) encrypted on-chip bus architecture for internet-of-things (IoT) system-on-chips (SoC)

Abstract: OF THE DISSERTATION A HIGH PERFORMANCE ADVANCED ENCRYPTION STANDARD (AES) ENCRYPTED ON-CHIP BUS ARCHITECTURE FOR INTERNET-OF-THINGS (IOT) SYSTEM-ON-CHIPS (SOC) by Xiaokun Yang Florida International University, 2016 Miami, Florida Professor Jean H. Andrian, Major Professor With industry expectations of billions of Internet-connected things, commonly referred to as the IoT, we see a growing demand for high-performance on-chip bus architectures with the following attributes: small scale, low energy, high security, and highly configurable structures for integration, verification, and performance estimation. Our research thus mainly focuses on addressing these key problems and finding the balance among all these requirements that often work against each other. First of all, we proposed a low-cost and low-power System-on-Chips (SoCs) architecture (IBUS) that can frame data transfers differently. The IBUS protocol provides two novel transfer modes the block and state modes, and is also backward compatible with the conventional linear mode. In order to evaluate the bus performance automatically and accurately, we also proposed an evaluation methodology based on the standard circuit design flow. Experimental results show that the IBUS based design uses the least hardware resource and reduces energy consumption to a half of an AMBA Advanced High-Performance Bus (AHB) and Advanced eXensible Interface (AXI). Additionally, the valid bandwidth of the IBUS based design is 2.3 and 1.6 times, respectively, compared with the AHB and AXI based implementations.

Samsung display co ltd

Abstract: A display device includes a data request unit in a frame rate controller, and requires and transmits necessary data for the frame data buffer receiving and storing the image data of an entire pixel area and the rest of the frame rate controllers. In a case of a motion picture that is moved among a plurality of display areas, the image data corresponding to a plurality of regions is transmitted from the frame data buffer or a plurality of frame rate controllers, and in a case of the motion picture that is moved between neighboring pixel areas, the image data of the neighboring pixel area is transmitted from the frame data buffer or the neighboring frame rate controller for processing. Accordingly, a fast-moving motion picture may be realized without the need for an additional memory.

Motion vector acquisition method, device, computer equipment and storage medium

Abstract: This application discloses a motion vector obtaining method and apparatus, a computer device, and a storage medium, and pertains to the field of video compression technologies. In the method, an initial motion vector of a to-be-processed picture block is determined by using a location relationship between a reference block and the to-be-processed picture block. When the reference block and the to-be-processed picture block are located in a same coding tree block, a decoder uses an initial motion vector of the reference block as the initial motion vector of the to-be-processed picture block. When the reference block and the to-be-processed picture block are located in different coding tree blocks, the decoder uses a final motion vector of the reference block as the initial motion vector of the to-be-processed picture block. In this case, when the final motion vector of the reference block is required for the to-be-processed picture block, the initial motion vector of the reference block may be used as the final motion vector of the reference block, so that the to-be-processed picture block can be used, thereby avoiding a case in which the to-be-processed picture block can be decoded only after the final motion vector of the reference block is obtained, and improving decoding efficiency.

Motion vector acquisition method and device, computer equipment and storage medium

Abstract: The invention discloses a motion vector acquisition method and device, computer equipment and a storage medium, and belongs to the technical field of video compression. The method comprises the following steps: an initial state motion vector of a to-be-processed image block is determined by utilizing a position relationship between a reference block and the to-be-processed image block; when the reference block and the to-be-processed image block are located in the same coding tree block, the decoder takes the initial state motion vector of the reference block as the initial state motion vectorof the to-be-processed image block; when the reference block and the to-be-processed image block are not located in the same coding tree block, the decoder uses the final state motion vector of the reference block as the initial state motion vector of the image block to be processed, when the to-be-processed image block needs the final state motion vector of the reference block, the initial statemotion vector of the reference block can be used as the final state motion vector of the reference block, so that the to-be-processed image block can be used conveniently, the situation that the to-be-processed image block can continue to be decoded until the reference block obtains the final state motion vector can be avoided, and the decoding efficiency is improved.