International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

International Symposium on Quality Electronic Design

We analyze Schmitt-Trigger (ST)-based differential-sensing static random access memory (SRAM) bitcells for ultralow-voltage operation. The ST-based SRAM bitcells address the fundamental conflicting design requirement of the read versus write operation of a conventional 6T bitcell. The ST operation gives better read-stability as well as better write-ability compared to the standard 6T bitcell. The proposed ST bitcells incorporate a built-in feedback mechanism, achieving process variation tolerance - a must for future nano-scaled technology nodes. A detailed comparison of different bitcells under iso-area condition shows that the ST-2 bitcell can operate at lower supply voltages. Measurement results on ten test-chips fabricated in 130-nm CMOS technology show that the proposed ST-2 bitcell gives 1.6× higher read static noise margin, 2× higher write-trip-point and 120-mV lower read-Vmin compared to the iso-area 6T bitcell.

Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design

This paper presents a novel single-ended disturb-free 9T subthreshold SRAM cell with cross-point data-aware Write word-line structure. The disturb-free feature facilitates bit-interleaving architecture, which can reduce multiple-bit upsets in a single word and enhance soft error immunity by employing Error Checking and Correction (ECC) technique. The proposed 9T SRAM cell is demonstrated by a 72 Kb SRAM macro with a Negative Bit-Line (NBL) Write-assist and an adaptive Read operation timing tracing circuit implemented in 65 nm low-leakage CMOS technology. Measured full Read and Write functionality is error free with VDD down to 0.35 V ( 0.15 V lower than the threshold voltage) with 229 KHz frequency and 4.05 μW power. Data is held down to 0.275 V with 2.29 μW Standby power. The minimum energy per operation is 4.5 pJ at 0.5 V. The 72 Kb SRAM macro has wide operation range from 1.2 V down to 0.35 V, with operating frequency of around 200 MHz for VDD around/above 1.0 V.

/pdf/a-single-ended-disturb-free-9t-subthreshold-sram-with-cross-221sd28qry.pdf

A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing

Since Moore’s law driven scaling of planar MOSFETs
faces formidable challenges in the nanometer regime, FinFETs and Trigate FETs have emerged as their successors. Owing
to the presence of multiple (two/three) gates, FinFETs/Trigate
FETs are able to tackle short-channel effects (SCEs) better than
conventional planar MOSFETs at deeply scaled technology nodes
and thus enable continued transistor scaling. In this paper, we
review research on FinFETs from the bottommost device level
to the topmost architecture level. We survey different types of
FinFETs, various possible FinFET asymmetries and their impact,
and novel logic-level and architecture-level tradeoffs offered by
FinFETs. We also review analysis and optimization tools that
are available for characterizing FinFET devices, circuits, and
architectures.

/pdf/finfets-from-devices-to-architectures-3wvjf3zgcz.pdf

FinFETs: From Devices to Architectures

Data stability of SRAM cells has become an important issue with the scaling of CMOS technology. Memory banks are also important sources of leakage since the majority of transistors are utilized for on-chip caches in today's high performance microprocessors. A new nine-transistor (9T) SRAM cell is proposed in this paper for simultaneously reducing leakage power and enhancing data stability. The proposed 9T SRAM cell completely isolates the data from the bit lines during a read operation. The read static-noise-margin of the proposed circuit is thereby enhanced by 2 X as compared to a conventional six-transistor (6T) SRAM cell. The idle 9T SRAM cells are placed into a super cutoff sleep mode, thereby reducing the leakage power consumption by 22.9% as compared to the standard 6T SRAM cells in a 65-nm CMOS technology. The leakage power reduction and read stability enhancement provided with the new circuit technique are also verified under process parameter variations.

Characterization of a Novel Nine-Transistor SRAM Cell

Data stability of static random access memory (SRAM) circuits has become an important issue with the scaling of CMOS technology Memory arrays are also an important source of leakage since the majority of transistors are utilized for on-chip caches in today's high performance microprocessors Two six transistor SRAM cells based on independent-gate FinFET technology (IG-FinFET) are described in this paper for simultaneously reducing the active and standby mode power consumption while enhancing the data stability and the integration density With the first independent-gate FinFET SRAM cell, one gate of each double-gate access and pull-up transistor is permanently disabled in order to enhance the data stability while achieving write-ability with minimum sized transistors With the second independent-gate FinFET SRAM cell, the threshold voltages of the access transistors are dynamically adjusted during circuit operation in order to maximize the memory integration density without sacrificing the performance and stability The read stability is enhanced by up to 92% with the IG-FinFET SRAM cells as compared to a tied- gate FinFET SRAM cell with the same size transistors in a 32 nm FinFET technology Furthermore, with the IG-FinFET SRAM cells, the idle mode leakage power and the cell area are reduced by up to 36% and 11%, respectively, as compared to a standard tied-gate FinFET SRAM cell sized for comparable read stability in a 32 nm FinFET technology

Independent-gate and tied-gate FinFET SRAM Circuits: Design guidelines for reduced area and enhanced stability

Temperature-dependent subthreshold and gate-oxide leakage power characteristics of domino logic circuits under the influence of process parameter variations are evaluated in this paper. Preferred input vectors and node voltage states that minimize the total leakage power consumption are identified at the lower and upper extremes of a typical die temperature spectrum. New low-leakage circuit design guidelines are presented based on the results. Significantly increased gate dielectric tunneling current, as described in this paper, dramatically changes the leakage power characteristics of dynamic circuits in deeply scaled nanometer CMOS technologies. Contrary to the previously published techniques, a charged dynamic-node voltage state with low inputs is preferred for reducing the total leakage power consumption in the most widely used types of single- and dual-threshold voltage domino gates, particularly at low die temperatures. Furthermore, leakage power savings provided by the dual-threshold voltage domino logic circuit techniques based on input gating are all together reduced due to the significance of gate dielectric tunneling in sub-45-nm CMOS technologies

Leakage Power Characteristics of Dynamic Circuits in Nanometer CMOS Technologies

Data in conventional six transistor (6T) static random access memory (SRAM) cells are vulnerable to noise due to the direct access to the data storage nodes through the bit lines during a read operation. A new nine transistor (9T) SRAM cell is proposed in this paper for simultaneously enhancing read stability and reducing leakage power consumption. The proposed 9T SRAM cell isolates the data from the bit lines during a read operation. The read static-noise-margin (SNM) of the proposed circuit is enhanced by 2times as compared to a standard 6T SRAM cell in a 65 nm CMOS technology. Furthermore, leakage power consumption of the new 9T SRAM cell is reduced by 22.9% as compared to the 6T SRAM cell. The read stability enhancement and leakage power reduction provided by the new circuit technique are also verified under process parameter variations.

High Read Stability and Low Leakage Cache Memory Cell

In the sub-65 nm CMOS technologies, subthreshold and gate dielectric leakage currents need to be simultaneously suppressed for effective energy reduction. New low-leakage circuit techniques based on multi-threshold-voltage (multi-Vt) and multi-oxide-thickness (multi-tox) standard single-gate and emerging double-gate MOSFET/FinFET technologies are presented in this paper. The leakage savings achieved with the techniques are characterized for a diverse set of logic and memory circuits that are widely used in systems-on-chips. The speed, active power, noise immunity, and area tradeoffs with the leakage reduction schemes are also evaluated.

Zhiyu Liu

Papers

Characterization of a Novel Nine-Transistor SRAM Cell

Independent-gate and tied-gate FinFET SRAM Circuits: Design guidelines for reduced area and enhanced stability

Leakage Power Characteristics of Dynamic Circuits in Nanometer CMOS Technologies

High Read Stability and Low Leakage Cache Memory Cell

Leakage-Aware Design of Nanometer SoC