Author
Zhonghua Yu
Bio: Zhonghua Yu is an academic researcher from Peking University. The author has contributed to research in topics: Quantum tunnelling & Field-effect transistor. The author has an hindex of 2, co-authored 2 publications receiving 16 citations.
Papers
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TL;DR: In this paper, a compact model for double-gate tunnel FETs (TFETs) with gate-drain underlap (DG u-TFET) is proposed which accounts for the alleviation of ambipolar current and Miller capacitance.
Abstract: A compact model for double-gate tunnel FETs (TFETs) with gate–drain underlap (DG u-TFET) is proposed which accounts for the alleviation of ambipolar current and Miller capacitance ( ${C}_{\textrm {dg}}$ ) compared with double-gate tunnel FETs (DG TFET). The ON-state current degradation caused by the underlap is reproduced by extending the ideal DG TFET model with an effective resistance between the channel and the drain. Based on the device surface potential, the terminal charge model is developed which enables the possibility of circuit simulation and the terminal capacitance is further derived from the definition. This model captures the electrical characteristics of DG u-TFET explicitly and good agreement is achieved compared with TCAD simulation. After the model is implemented into HSPICE, an inverter is established and successfully simulated without convergence problem.
14 citations
09 May 2016
TL;DR: In this paper, an asymmetric gate oxide and source pocket double-gate tunneling FET (DG TFET) structure is proposed to enchance the current drive, which has steeper average sub-threshold swing (SS), larger on currents, smaller supply voltage.
Abstract: In this paper, asymmetric gate oxide and source pocket double-gate tunneling FET (DG TFET) structure is proposed to enchance the current drive. Compared with conventional DG-TFET, the propsed TFET has steeper average subthreshold swing (SS), larger on currents, smaller supply voltage. The resason of improvements is mainly attributed to the enhanced tunneling electric field high-k gate oxide brings and larger tunneling area cuased by the source pocket.
6 citations
TL;DR: In this article , a normal contact electrification between an insulator particle and metal surface is modeled as an attempt to explore methods for the valuations of the critical gap and charging efficiency.
TL;DR: In this article , a PbSe quantum dot-doped-mode-locked fiber laser is experimentally demonstrated with a stable pulse train with a pulse duration of 36 ps, a pulse repetition rate of 4.5 MHz, and an average laser power of 9.8 mW under the pump power of 800 mW.
Abstract: Herein, a PbSe quantum dot-doped-mode-locked fiber laser is experimentally demonstrated. A PbSe quantum dot-doped fiber is prepared using a melting method and induced as a gain medium in our mode-locked fiber laser. By increasing the pump power, a stable pulse train is obtained with a pulse duration of 36 ps, a pulse repetition rate of 4.5 MHz, an average laser power of 9.8 mW, and a central wavelength of 1214.5 nm. The pulse duration can be changed by adjusting the PC or increasing the pump power. The maximum laser power obtained was 42.7 mW under the pump power of 800 mW. Our results prove that a quantum dot-doped-mode-locked fiber laser is achievable, which provides a new scheme to solve wavelength problem of rare-earth-doped mode-locked fiber lasers.
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TL;DR: In this article, a compact model of source depletion, drain depletion and channel potential in the charge plasma based tunnel field effect transistor (U-CPBTFET) with two underlap regions (source-gate and gate-drain) is proposed and developed.
16 citations
TL;DR: This study focuses on the following four challenges from the perspective of circuit design: the uncontrollable forward p-i-n current; the relatively low on-current; the delayed output saturation; the non-shareable active area in the layout and some structures and specific circuit design suggestions separately.
Abstract: Steep sub-threshold interband tunnel field-effect transistors (TFETs) are promising candidates for low-supply voltage applications with better performance than the traditional complementary metal oxide semiconductor (CMOS). However, some of the shortcomings of TFETs also severely limit their application. From the device perspective, studies have been conducted on TFETs in order to improve their performance. Instead, this study focuses on the following four challenges from the perspective of circuit design: (1) the uncontrollable forward p-i-n current; (2) the relatively low on-current; (3) the delayed output saturation; (4) the non-shareable active area in the layout. We conduct comprehensive simulations on various circuits with TFET to analyze these four challenges. Based on the analysis results and summarization of the previous solutions, we introduce some structures and offer specific circuit design suggestions separately, not only letting the TFET circuit designer know the technologies, but also clearly showing the possible cost.
14 citations
TL;DR: In this paper, an analytical model of dual material single gate doping-less tunnel FET (DM-GU-TFET) with gate underlap regions has been proposed and the potential of gate under-lap area with channel area has been examined using modeling and the results are validated using TCAD simulation at boundary conditions.
12 citations
TL;DR: In this article, the impact of low-k gate oxide material on the ambipolarity of SOI-DG TFET was analyzed based on the primary DC characterisation of the proposed device.
Abstract: This work exclusively illustrates the impact of low-k gate oxide material on the ambipolarity of SOI-DG TFET proposed previously in literature (Goswami and Bhowmick in Silicon, https://doi.org/10.1007/s12633-019-00169-7
, 2019) with a comparative AC analysis of the two TFET architectures presented here. Based upon the primary DC characterisation of the proposed device, a thorough analysis of ambipolarity, impact of varying mole fraction, influence of temperature on device characteristics are performed explicitly. For the complete RF characterisation, the transconductance, cut-off frequency, transit time, power delay product, transconductance generation efficiency and parasitic capacitances are presented in detail with a comparative summarization. The reasonably high on-current of the proposed device (orders of mA/μm) with very low leakage current floor (orders of fA/μm) makes the device suitable for low power applications as well as for high fan-out operations. The seemingly low threshold voltage with notably low VDD values (0.3 V) aids to substantial reduction of dynamic power consumption. The high cut off frequency (best reported in tera hertz) of the device opens the window for numerous diversified applications.
11 citations
TL;DR: In this paper, a dielectric modulated gate underlap dopingless tunnel field effect transistor (DM-GUD-TFET) was proposed for biomedical applications, where a cavity was introduced on side of the gate metal to attain high sensitivity for biomedical application.
Abstract: The present paper has proposed a dielectric modulated gate underlap dopingless tunnel field effect transistor (DM-GUD-TFET). In the proposed device, a cavity is introduced on side of the gate metal to attain high sensitivity for biomedical applications. The immobilization of biomolecules within the cavity induces the variation in surface potential. The present work has analyzed different parameters affecting the electrical characteristics of the device which include a change in spacer length, variation in applied voltages (Vds and Vgs), and channel material. The modeling output characteristics have been compared with simulated outcomes for validating results. The potential model is obtained by categorizing the structure into ten sections counting source-drain depleted sections. The surface potential of each section is resolved using 1-dimennsional and 2-dimensional Poisson’s eq. (P.Eq.), respectively. The different values of dielectric constant and charge density are used for recreating the biomolecules for simulation in Silvaco ATLAS tool.
10 citations