Zhuo Chao Sun

Bio: Zhuo Chao Sun is an academic researcher from Nanyang Technological University. The author has contributed to research in topics: Comparator & Effective number of bits. The author has an hindex of 4, co-authored 4 publications receiving 158 citations.

A 400 nW Single-Inductor Dual-Input–Tri-Output DC–DC Buck–Boost Converter With Maximum Power Point Tracking for Indoor Photovoltaic Energy Harvesting

Abstract: This paper presents a single-inductor dual-input–tri-output buck–boost (DITOBB) converter that manages energy harvesting, energy storage, and power rail regulation of an indoor remote sensor system. The converter operates in discontinuous conduction mode (DCM) and regulates the outputs with a combination of pulse-skipping modulation (PSM) and constant-on-time pulse-frequency modulation (PFM). To reduce the quiescent power, all the circuit blocks are turned off when the outputs are within regulation, except a system clock generator. A newly designed relaxation oscillator provides the main clock of the system, which requires neither reference voltages nor comparators. The frequency of the system clock doubles or halves based on the states of the sources and outputs following a proposed algorithm. The DITOBB converter has been designed and fabricated using $0.18\;\upmu \text{m}$ CMOS process. With a quiescent power of 400 nW, the designed DITOBB converter shows a measured peak efficiency of 83% at $100\;\upmu W$ output power.

A 1 V 103 dB 3rd-Order Audio Continuous-Time $\Delta \Sigma $ ADC With Enhanced Noise Shaping in 65 nm CMOS

Abstract: As technology scales, integrating high resolution ADCs into high fidelity mixed signal systems becomes challenging in advanced CMOS processes. Cascading integrators to achieve high-order filter structures limits the modulation index and compromises on stability at the expense of added hardware and power consumption. To optimize the maximum stable amplitude (MSA) to accommodate a larger input dynamic range, the supply rails have to be expanded, which limited technology choices to those of a larger feature size. This work proposes a 25 kHz 3rd-order continuous-time $\Delta \Sigma $ modulator (CT $\Delta \Sigma \text {M}$ ) utilizing a 5-bit SAR quantizer, enabling noise coupling (NC) to be possible in a typical nanoscale CMOS 65 nm technology with VDD of 1 V. Mismatches in SAR comparator and DAC array are mitigated with a proposed calibration scheme while CM mismatches are solved by a floating differential charge storage capacitor (FDCSC) coupling method. To allow sufficient time for SAR bit cycling and noise charge feedback settling, 1 Ts excess loop delay (ELD) is compensated with digital differentiation that minimizes both the power and complexity of the auxiliary feedback DAC. The prototype obtained DR/SNR/SNDR of 103.1 dB/100.1 dB/95.2 dB while dissipating 0.8 mW, hence achieving a FoMSNDR and FoMschreier of 0.34 pJ/level and 177.9 dB, respectively.

A 1.33 $\mu{\rm W}$ 8.02-ENOB 100 kS/s Successive Approximation ADC With Supply Reduction Technique for Implantable Retinal Prosthesis

Abstract: This paper presents a chip level 9 bits Charge Folding Successive-Approximation-Register (SAR) Analog-to-Digital Converter (ADC) to be used in a CMOS image sensor for retinal prosthesis. It has a maximum single-ended input range of 1.8 V but only uses a supply voltage of 0.9 V for the entire ADC through the Charge Folding method. Therefore, the input range is no longer limited by the supply rail as in conventional SAR ADC. Moreover, the ADC is controlled by an internal delay line based Asynchronous Clock Generator which can be programmed to adjust the resolution of the ADC from 5 to 9 bits. Therefore, resolution adaptation function can be applied to improve the energy efficiency up to 15%. The test chip is implemented in 0.18 $\mu{\rm m}$ CMOS process and occupies an area of 0.15 ${\rm mm}^{2}$ . At 0.9 V and 100 kS/s, the 9 bit s ADC consumes 1.33 $\mu{\rm W}$ and achieves an energy efficiency of 51.3 fJ/conversion-step . In addition, the power consumption can be further reduced by scaling the supply voltage and sampling frequency. At 100 kS/s, this ADC is capable of converting the input signal at a rate equivalent to 30 frames/s for a pixel array up to 3200 pixels.

A 5.8 nW 9.1-ENOB 1-kS/s Local Asynchronous Successive Approximation Register ADC for Implantable Medical Device

Abstract: This brief presents a 10-bits successive approximation register analog-to-digital converter (ADC) with a sampling rate of 1 kS/s for implantable medical devices. This ADC is implemented in a 65-nm CMOS process in which leakage current will be a key design parameter. It imposes the highest degree of simplicity in the design of the ADCs architecture. Thus, the transistor count is minimized, which reduces not only the active power, but also the number of leakage sources. The modified top-plate V cm -based switching offers energy efficient switching at the capacitive-DAC (CDAC) and uses simple control logic. In addition, the proposed asymmetrical metal-oxide-metal capacitor reduces the size of the CDAC by 90% for a given gain error. Furthermore, the input referred offset voltage of the dynamic comparator can be improved by the top-plate V cm -based switching method at system level without using any additional transistor. The other building blocks are also simplified for lower power consumption. This ADC occupies an area of 0.046 mm 2 . At 0.9 V and 1 kS/s, the 10-bits ADC consumes 5.8 nW, in which, 2.34 nW is contributed by leakage power consumption. The ADC achieves 9.1-ENOB and an energy efficiency of 10.94-fJ/conversion step.

An Ultra-Low Power Fully Integrated Energy Harvester Based on Self-Oscillating Switched-Capacitor Voltage Doubler

Abstract: This paper presents a fully integrated energy harvester that maintains >35% end-to-end efficiency when harvesting from a 0.84 mm 2 solar cell in low light condition of 260 lux, converting 7 nW input power from 250 mV to 4 V. Newly proposed self-oscillating switched-capacitor (SC) DC-DC voltage doublers are cascaded to form a complete harvester, with configurable overall conversion ratio from 9× to 23×. In each voltage doubler, the oscillator is completely internalized within the SC network, eliminating clock generation and level shifting power overheads. A single doubler has >70% measured efficiency across 1 nA to 0.35 mA output current ( >10 5 range) with low idle power consumption of 170 pW. In the harvester, each doubler has independent frequency modulation to maintain its optimum conversion efficiency, enabling optimization of harvester overall conversion efficiency. A leakage-based delay element provides energy-efficient frequency control over a wide range, enabling low idle power consumption and a wide load range with optimum conversion efficiency. The harvester delivers 5 nW-5 μW output power with >40% efficiency and has an idle power consumption 3 nW, in test chip fabricated in 0.18 μm CMOS technology.

A 10 nW–1 $\upmu {\rm{W}}$ Power Management IC With Integrated Battery Management and Self-Startup for Energy Harvesting Applications

Abstract: This paper presents a 10 nW–1 $\upmu{\rm{W}}$ power management IC with 3.2 nW quiescent power consumption for solar energy harvesting applications. The chip integrates a switch matrix that can be configured as a buck or a boost dc–dc converter using a single inductor as well as output voltage regulation logic, battery management block, and self-startup. The control circuit of the converter is designed in an asynchronous fashion that scales the effective switching frequency of the converter with the level of power transferred. The on-time of the converter switches adapts dynamically to the input and output voltages for peak-current control and zero-current switching. For input power of 500 nW, the proposed chip achieves an efficiency of 82%, including the control circuit overhead, while charging the energy storage device at 3 V from 0.5 V input. In buck mode, it achieves a peak efficiency of 87% and maintains efficiency greater than 80% for output power of 50 nW–1 $\upmu{\rm{W}}$ with input voltage of 3 V and output voltage of 1 V.

MISIMO: A Multi-Input Single-Inductor Multi-Output Energy Harvesting Platform in 28-nm FDSOI for Powering Net-Zero-Energy Systems

Abstract: This paper presents a power management unit that meets the need of small-form-factor net-zero energy systems by aggregating the maximum available power from three different energy sources while simultaneously regulating three output power rails over a wide dynamic load range, while also managing the charging and discharging of a battery, all in a single-stage single-inductor converter The proposed architecture uses hysteresis control to regulate the voltage of each harvester at their respective maximum power points (MPPs) using pulse-frequency modulation (PFM) and adaptive inductor ON-time, all via a low-power event-driven controller The converter, fabricated in 28-nm fully-depleted silicon-on-insulator (FDSOI), achieves a peak efficiency of 89% and supports an output power range from $1~\mu \text{W}$ to 60 mW with efficiency >75% at $V_{\text {out}}=1$ V and >69% at $V_{\text {out}}=06-09$ V, all with a quiescent power of only 262 nW

Single-Inductor Multi-Input Multi-Output DC–DC Converter With High Flexibility and Simple Control

Abstract: Multi-input multi-output (MIMO) dc–dc converters can integrate multiple input sources and output loads simultaneously. This article proposes a new single-inductor MIMO dc–dc converter with a wide conversion ratio. The proposed converter allows input sources to be added or removed seamlessly with no cross-regulation problem. Meanwhile, the outputs are independently controlled, i.e., the load change at one output cell will not affect the other interconnected output cells. Constant current control is the main control requirement. When constant current control is applied to all input cells, the power provided by each input source is proportional to the voltage magnitude of the source. When the constant current control is applied to some of the input cells, the input sources with direct duty-cycle controlled input cells can provide specific power through controlling the duty cycles of the switches of the corresponding input cells. Moreover, the switching time of switches is irrelevant. Therefore, it is easy to realize the high extension capability for arbitrary inputs/outputs. A dual-input dual-output prototype is constructed to illustrate the performance of the proposed converter. The corresponding component design is presented.

A Dynamic Zoom ADC With 109-dB DR for Audio Applications

Abstract: This paper presents the first dynamic zoom ADC. Intended for audio applications, it achieves 109-dB DR, 106-dB signal-to-noise ratio, and 103-dB SNDR in a 20-kHz bandwidth, while dissipating only 1.12 mW. This translates into the state-of-the-art energy efficiency as expressed by a Schreier FoM of 181.5 dB. It also achieves the state-of-the-art area efficiency, occupying only 0.16 mm2 in the 0.16- $\mu \text{m}$ CMOS. These advances are enabled by the use of concurrent fine and coarse conversions, dynamic error-correction techniques, and a dynamically biased inverter-based operational transconductance amplifier.