Zuo-Min Tsai

Bio: Zuo-Min Tsai is an academic researcher from National Chung Cheng University. The author has contributed to research in topics: Amplifier & CMOS. The author has an hindex of 23, co-authored 103 publications receiving 1711 citations. Previous affiliations of Zuo-Min Tsai include National Taiwan University.

Design and analysis for a miniature CMOS SPDT switch using body-floating technique to improve power performance

Abstract: A low insertion-loss single-pole double-throw switch in a standard 0.18-/spl mu/m complementary metal-oxide semiconductor (CMOS) process was developed for 2.4- and 5.8-GHz wireless local area network applications. In order to increase the P/sub 1dB/, the body-floating circuit topology is implemented. A nonlinear CMOS model to predict the switch power performance is also developed. The series-shunt switch achieves a measured P/sub 1dB/ of 21.3 dBm, an insertion loss of 0.7 dB, and an isolation of 35 dB at 2.4 GHz, while at 5.8 GHz, the switch attains a measured P/sub 1dB/ of 20 dBm, an insertion loss of 1.1 dB, and an isolation of 27 dB. The effective chip size is only 0.03 mm/sup 2/. The measured data agree with the simulation results well, including the power-handling capability. To our knowledge, this study presents low insertion loss, high isolation, and good power performance with the smallest chip size among the previously reported 2.4- and 5.8-GHz CMOS switches.

Millimeter-Wave CMOS Power Amplifiers With High Output Power and Wideband Performances

Abstract: In this paper, we propose a design method of multi-way combining networks with impedance transformation for millimeter-wave (MMW) power amplifiers (PAs) to achieve high output power and wideband performance simultaneously in millimeter-wave frequency. Based on the proposed methodology, three power amplifiers are designed and fabricated in V-band, W-band, and D-band using 65-nm CMOS technology. With 1.2-V supply, the saturation powers of these power amplifiers are 23.2 dBm, 18 dBm and 13.2 dBm at 64 GHz, 90 GHz, and 140 GHz, with 25.1-GHz, 26-GHz, and 30-GHz 3-dB bandwidth, respectively. Compared with the published MMW amplifiers, these PAs achieve high output power and wide band performances simultaneously, and the ouput power levels is the state-of-the-art performance at these frequencies.

A Modified Wilkinson Power Divider With Isolation Bandwidth Improvement

Abstract: This paper proposes a novel modified Wilkinson power divider with wide isolation bandwidth The isolation bandwidth can be extended by an additional isolation network (INW) in the circuits An equal and an unequal 4-GHz modified Wilkinson power divider on FR4 with compact circuit sizes are designed and measured to verify the new design concept The measurement results show the operation bandwidth from 18 to 64 GHz with 20-dB isolation in the equal case In the unequal case, the operation frequency starts from 24 to 53 GHz with 20-dB isolation Moreover, a 3-GHz 1-to-3 modified Wilkinson power divider is realized with the operation frequency from 205 to 383 GHz with 20-dB isolation These circuits demonstrate that the isolation bandwidth can be extended by an INW, and this INW can be used in many power dividers with different applications To the authors' knowledge, these circuits provide the widest fractional bandwidth of isolation in a Wilkinson power divider ever reported, except those using multisection structures

A High-Range-Accuracy and High-Sensitivity Harmonic Radar Using Pulse Pseudorandom Code for Bee Searching

Abstract: This paper presents a 9.4/18.8-GHz harmonic radar to investigate the behavior of bees with colony collapse disorder. The challenges of using harmonic radar for bee searching include the requirements of high range accuracy and high sensitivity. A new harmonic radar using the pseudorandom code positioning technique to simultaneously achieve high range accuracy and high sensitivity is proposed. This study also proposes a new method to cancel the local leakage to further improve sensitivity. To realize the transponder, a compact antenna is designed using the topology characteristics of the composite right/left-handed transmission-line concept. The measured sensitivity of the transceiver is -120 dBm, which is 27 dB lower than the noise level. Field testing results demonstrate a 60-m detection range within 1-m distance error with 1.75-W transmitting power. The significant improvement of the sensitivity and the range accuracy reveal the advantages of applying the code-positioning technique to the harmonic radar.

Broadband Balanced Frequency Doublers With Fundamental Rejection Enhancement Using a Novel Compensated Marchand Balun

Abstract: In this paper, a novel compensation technique is proposed to improve the imbalance of a Marchand balun due to the unequal odd- and even-mode phase velocities of the coupled lines. Using this method, the fundamental rejection of the balanced doubler with the Marchand balun can be effectively enhanced. Two single-balanced doublers using the improved Marchand balun are designed, fabricated, and measured to verify the concept in CMOS processes. One doubler for 15–36-GHz possesses $-$ 10-dB conversion gain with the 3-dB bandwidth of 82.4% and the fundamental rejection of 33 dB. The other doubler for 95–150 GHz achieves $-$ 7.9-dB conversion gain with the 3-dB bandwidth of 45% and the fundamental rejection of 30 dB. With the proposed compensation technique, these frequency doublers feature wide bandwidths and high fundamental rejections.

IEEE Transactions on Microwave Theory and Techniques and Antennas and Propagation Announce a Joint Special Issue on Ultra-Wideband (UWB) Technology

Abstract: Before the emergence of ultra-wideband (UWB) radios, widely used wireless communications were based on sinusoidal carriers, and impulse technologies were employed only in specific applications (e.g. radar). In 2002, the Federal Communication Commission (FCC) allowed unlicensed operation between 3.1–10.6 GHz for UWB communication, using a wideband signal format with a low EIRP level (−41.3dBm/MHz). UWB communication systems then emerged as an alternative to narrowband systems and significant effort in this area has been invested at the regulatory, commercial, and research levels.

The last barrier: on-chip antennas

Abstract: This paper has presented a comprehensive overview of on-chip antennas, which remain the last bottleneck for achieving true SoC RF solutions. CMOS remains the mainstream IC technology choice but is not well suited for on-chip antennas, requiring the use of innovative design techniques to overcome its shortcomings. Codesign of circuits and antennas provide leverage to the designer to achieve optimum performance. The layout of on-chip antennas is dictated by foundry specific rules whereas characterization of on-chip antennas requires special text fixtures. For future highly integrated SoC solutions, foundries will have to provide special layers for efficient on-chip antenna implementations, as they currently do for on-chip inductors. In many of the emerging applications such as THz communication, implantable systems and energy harvesting, on-chip antennas have shown immense potential and are likely to play a major role in shaping up future communication systems.

Analysis and Design of Stacked-FET Millimeter-Wave Power Amplifiers

Abstract: Stacked field-effect transistor (FET) CMOS millimeter-wave power amplfiers (PAs) are studied with a focus on design of appropriate complex impedances between the transistors. The stacking of multiple FETs allows increasing the supply voltage, which, in turn, allows higher output power and a broader bandwidth output matching network. Different matching techniques for the intermediate nodes are analyzed and used in two-, three-, and four-stack single-stage $Q$ -band CMOS PAs. A four-stack amplifier design achieves a saturated output power greater than 21 dBm while achieving a maximum power-added efficiency (PAE) greater than 20% from 38 to 47 GHz. The effectiveness of an inductive tuning technique is demonstrated in measurement, improving the PAE from 26% to 32% in a two-stack PA design. The input and output matching networks are designed using on-chip shielded coplanar waveguide transmission lines, as well as metal finger capacitors. The amplifiers were implemented in a 45-nm CMOS silicon-on-insulator process. Each of the amplifiers occupies an area of 600 $\mu$ m $\,\times\,$ 500 $\mu$ m including pads.

A Watt-Level Stacked-FET Linear Power Amplifier in Silicon-on-Insulator CMOS

Abstract: A single-stage stacked field-effect transistor (FET) linear power amplifier (PA) is demonstrated using 0.28-?m 2.5-V standard I/O FETs in a 0.13-?m silicon-on-insulator (SOI) CMOS technology. To overcome the low breakdown voltage limit of MOSFETs, a stacked-FET structure is employed, where four transistors are connected in series so that their output voltage swings are added in phase. With a 6.5-V supply, the measured PA achieves a small-signal gain of 14.6 dB, a saturated output power of 32.4 dBm, and a maximum power-added efficiency (PAE) of 47% at 1.9 GHz. Using a reverse-link IS-95 code division multiple access modulated signal, the PA shows an average output power of up to 28.7 dBm with a PAE of 41.2% while meeting the adjacent channel power ratio requirement. Using an uplink wideband code division multiple access modulated signal, the PA shows an average output power of up to 29.4 dBm with a PAE of 41.4% while meeting the adjacent channel leakage ratio requirement. The stacked-FET PA is designed to withstand up to 9 V of supply voltage before reaching its breakdown limit. This is the first reported stacked-FET linear PA in submicrometer SOI CMOS technology that delivers watt-level output power in the gigahertz frequency range with efficiency and linearity performance comparable to those of GaAs-based PAs.

On-chip integrated antenna structures in CMOS for 60 GHz WPAN systems

Abstract: This paper presents several on-chip antenna structures that may be fabricated with standard CMOS technology for use at millimeter wave frequencies. On-chip antennas for wireless personal area networks (WPANs) promise to reduce interconnection losses and greatly reduce wireless transceiver costs, while providing unprecedented flexibility for device manufacturers. This paper presents the current state of research in on-chip integrated antennas, highlights several pitfalls and challenges for on-chip design, modeling, and measurement, and proposes several antenna structures that derive from the microwave microstrip and amateur radio art. This paper also describes an experimental test apparatus for performing measurements on RFIC systems with on-chip antennas developed at The University of Texas at Austin.