Showing papers presented at "Asia and South Pacific Design Automation Conference in 2002"

Digital Watermarking

Abstract: Summary form only given. The ability to represent audio and video digitally and its vast popularity poses enormous challenges in protection against unauthorized use, copy and distribution in open, highly uncontrolled Internet environment. Digital watermarking, a technology for insertion of imperceptible information into multimedia content offers a solution for authentication and suitable action thereof. This is a rapidly maturing technology. Initiatives within the industry are ongoing for various forms of multimedia. Technology alone is unlikely to address all the copy protection issues. Business models and legal support also play an important role in tackling them.

Battery-Driven System Design: A New Frontier in Low Power Design

Abstract: As an increasing number of electronic systems are powered by batteries, battery life becomes a primary design consideration. Maxiimizing battery life requires system designers to develop an understanding of the capabilities and limitations of the batteries that power such systems, and to incorporate battery considerations into the system design process. Recent research has shown that, the amount of energy that can be supplied by a given battery varies significantly, depending on how the energy is drawn. Consequently, researchers are attempting to develop new battery-driven approaches to system design, which deliver battery life improvements over and beyond what can be achieved through conventional low-power design techniques. This paper presents an introduction to this emerging area, surveys promising technologies that have been developed for battery modeling and battery-efficient system design, and outlines emerging industry standards for smart battery systems.

Static and Dynamic Variable Voltage Scheduling Algorithms for Real-Time Heterogeneous Distributed Embedded Systems

Abstract: This paper addresses the problem of static and dynamic variable voltage scheduling of multi-rate periodic task graphs (i.e., tasks with precedence relationships) and aperiodic tasks in heterogeneous distributed real-time embedded systems. Such an embedded system may contain general-purpose processors, field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs). Variable voltage scheduling is performed only on general-purpose processors. The static scheduling algorithm constructs a variable voltage schedule via heuristics based on critical path analysis and task execution order refinement. The algorithm redistributes the slack in the initial schedule and refines task execution order in an efficient manner. The variable voltage schedule guarantees all the hard deadlines and precedence relationships of periodic tasks. The dynamic scheduling algorithm is also based on an initially valid static schedule. The objective of the on-line scheduling algorithm is to provide best-effort service to soft aperiodic tasks, as well as to reduce the system power consumption by determining clock frequencies (and correspondingly supply voltages) for different tasks at run-time, while still guaranteeing the deadlines and precedence relationships of hard real-time periodic tasks.

RTL-Datapath Verification using Integer Linear Programming

Abstract: Satisfiability of complex word-level formulas often arises as a problem in formal verification of hardware designs described at the register transfer level (RTL). Even though most designs are described in a hardware description language (HDL), like Verilog or VHDL, usually this problem is solved in the Boolean domain, using Boolean solvers. These engines often show a poor performance for data path verification. Instead of solving the problem at the bit-level, a method is proposed to transform conjunctions of bitvector equalities and inequalities into sets of integer linear arithmetic constraints. It is shown that it is possible to correctly model the modulo semantics of HDL operators as linear constraints. Integer linear constraint solvers are used as a decision procedure for bitvector arithmetic. In the implementation we focus on verification of arithmetic properties of Verilog-HDL designs. Experimental results show considerable performance advantages over high-end Boolean SAT solver approaches. The speed-up on the benchmarks studied is several orders of magnitude.

Evaluating Run-Time Techniques for Leakage Power Reduction

Abstract: While some leakage power reduction techniques require modification of process technology achieving savings at the fabrication stage, others are based on circuit-level optimizations and are applied at run-time. We focus our study on the latter kind and compare three techniques: input vector control, body bias control and power supply gating. We determine their limits and benefits, in terms of the potential leakage reduction, performance penalty and area and power overhead. The importance of the 'minimum idle time' parameter, as an additional evaluation tool, is emphasized, as well as the feasibility of achieving power supply gating at low levels of granularity. The obtained data supports the formulation of a comprehensive leakage reduction scheme, in which each technique is targeted for certain types of functional units and a given level of granularity depending on the incurred overhead cost and the obtainable savings.

Architecture Implementation Using the Machine Description Language LISA

Abstract: The development of application specific instruction set processors comprises several design phases: architecture exploration, software tools design, system verification and design implementation. The LISA processor design platform (LPDP) based on machine descriptions in the LISA language provides one common environment for these design phases. Required software tools for architecture exploration and application development can be generated from one sole specification. This paper focuses on the implementation phase and the generation of synthesizable HDL code from a LISA model. The derivation of the architectural structure, decoder and even approaches for the implementation of the data path are presented. Moreover the synthesis results of a generated and a handwritten implementation of a low-power DVB-T post processing unit are compared.

Hardware-Software Co-Synthesis of Low Power Real-Time Distributed Embedded Systems with Dynamically Reconfigurable FPGAs

Abstract: In this paper, we present a multi-objective hardware-software co-synthesis system for multi-rate, real-time, low power distributed embedded systems consisting of dynamically reconfigurable FPGAs, processors, and other system resources. We use an evolutionary algorithm based framework for automatically determining the quantity and type of different system resources, and then assigning tasks to different processing elements (PEs) and task communications to communication links. For FPGAs, we propose a two-dimensional, multi-rate cyclic scheduling algorithm, which determines task priorities based on real-time constraints and reconfiguration overhead information, and then schedules tasks based on the resource utilization and reconfiguration condition in both space and time. The FPGA scheduler is integrated in a list-based system scheduler. To the best of our knowledge, this is the first multi-objective co-synthesis system, which uses dynamically reconfigurable devices to synthesize a distributed embedded system, to target simultaneous optimization of system price and power. Experimental results indicate that our method can reduce schedule length by an average of 41.0% and reconfiguration power by an average of 46.0% compared to the previous method. It also yields multiple system architectures which trade off system price and power under real-time constraints.

System-level point-to-point communication synthesis using floorplanning information [SoC]

Abstract: In this paper, we present a point-to-point (P2P) communication synthesis methodology for system-on-chip (SOC) design. We consider real-time systems where IP selection, mapping and task scheduling are already fixed. Our algorithm takes the communication task graph (CTG) and IP sizes as inputs and automatically synthesizes a P2P communication network, which satisfies the specified deadlines of the application. As the main contribution, we first formulate the problem of automatic bitwidth synthesis which minimizes total wirelength and then propose an efficient heuristic to solve it. A key element in our approach is a communication-driven floorplanner which considers the communication energy consumption in the objective function. Experimental results show that, compared to standard shared bus architecture, significant power savings can be achieved by using the P2P scheme and communication-driven floorplanning. For instance, for an H.263 encoder we estimate 21.6% savings in energy and 15.1% in terms of wiring resources with an area overhead of only 4%.

On Test Scheduling for Core-Based SOCs

Abstract: We present a mathematical model for the problem of scheduling tests for core-based system-on-chip (SOC) VLSI designs. Given a set of tests for each core in the SOC and a set of test resources (e.g., test access mechanisms (TAM)), we determine the test plan for the application of the tests to the SOC. Test planning in this paper refers to the combined activities of test access architecture partitioning and test scheduling. These activities must be performed in conjunction as the choice of the test access architecture influences the test schedule. We justify the formulation of test scheduling w.r.t. minimum average completion time criterion as compared to minimum makespan. We show that then the problem of scheduling tests on TAMs can be mapped onto a graph theoretic problem which has a polynomial time optimal solution. We have implemented our algorithm as a test planner tool TPLAN. We present the theoretical analysis of our approach in this paper, and compare our results against those published earlier using integer linear programming techniques with encouraging results.

Electromigration Avoidance in Analog Circuits: Two Methodologies for Current-Driven Routing

Abstract: Interconnect with an insufficient width may be subject to electromigration and eventually cause the failure of the circuit at any time during its lifetime. This problem has gotten worse over the last couple of years due to the ongoing reduction of circuit feature sizes. For this reason, it is becoming crucial to address the problems of current densities and electromigration during layout generation. Here we present two new methodologies capable of routing analog multi-terminal signal nets with current-driven wire widths. Our first approach computes a Steiner tree layout satisfying all specified current constraints before performing a DRC- and current-correct point-to-point detailed routing. The second methodology is based on a terminal tree which defines a detailed terminal-to-terminal routing sequence. We also discuss successful applications of both methodologies in commercial analog circuits.

Improved Algorithms for Constructive Multi-Phase Test Point Insertion for Scan Based BIST

Abstract: New test point selection algorithms to improve test point insertion quality and performance of a multi-phase test point insertion scheme, while reducing the memory requirement of the analysis are proposed. A new memory efficient probabilistic fault simulation method, which also handles the reconvergences to a limited extent for increased accuracy, is introduced. Synergistic control point insertion is targeted for higher test point insertion quality. Experiments conducted on various large industrial circuits demonstrate the effectiveness of the new algorithms.

Leakage Power Estimation for Deep Submicron Circuits in an ASIC Design Environment

Abstract: Static power dissipation due to leakage current in transistors constitutes an increasing fraction of the total power in modern semiconductor technologies. Current technology trends indicate that the leakage contribution will increase rapidly. Developing power efficient products will require consideration of static power in early phases of design development. Design houses that use RTL synthesis based flow for designing ASICs require a quick and reasonably accurate estimate of static power dissipation. This is important for making early packaging decisions and planning the power grid. Keeping this in view, we propose a simple model which enables estimation of static power early in the design phase. Our model is based on the experimental data obtained from simulations at the design level: ln P/sub leak//sup lib/=S/sup lib/ ln Cells+C/sup lib/, where S/sup lib/ and C/sup lib/ are the technology-dependent slope and intercept parameters of the model and "Cells" is the number of cells in the design. The model is validated for a large benchmark circuit and the leakage power predicted by our model is within 2% of the actual leakage power predicted by a popular tool used in the industry.

Compiler-Directed Array Interleaving for Reducing Energy in Multi-Bank Memories

Abstract: With the increased use of embedded/portable devices such as smart cellular phones, pagers, PDAs, hand-held computers, and CD players, improving energy efficiency is becoming a critical issue. To develop a truly energy-efficient system, energy constraints should be taken into account early, in the design process; i.e., at the source level in software compilation and behavioral level in hardware compilation. Source-level optimizations are particularly important in data-dominated media applications that have become pervasive in energy-constrained mobile environments. This paper focuses on improving the effectiveness of energy savings from using multiple low-power operating modes provided in current memory modules. We propose a source level data space transformation technique called array interleaving that colocates simultaneously used array elements in a small set of memory modules. We validate the effectiveness of this transformation using a set of array-dominated benchmarks and observe significant savings in memory energy.

Improved SAT-based Bounded Reachability Analysis

Abstract: Symbolic simulation is widely used in logic verification. Previous approaches based on BDDs suffer from space outs, while SAT-based approaches have been found fairly robust. We propose a SAT-based symbolic simulation algorithm using a noncanonical two-input AND/INVERTER graph representation and on-the-fly reduction algorithm on such a graph representation. Unlike previous approaches where circuit is explicitly unrolled, we propagate the symbolic values represented using the simplified AND/INVERTER graph across the time frames. This simplification have significant impact on the performance of SAT-solver. Experimental results on large examples show the effectiveness of the proposed technique over previous approaches. Specifically we were able to find real bugs in pieces of the designs from IBM Gigahertz Processor Project which were previously remained undetected. Moreover, previous heuristics used in BDD-based symbolic simulation can still be applied to this algorithm.

Mode Selection and Mode-Dependency Modeling for Power-Aware Embedded Systems

Abstract: Among the techniques for system-level power management, it is not currently possible to guarantee timing constraints and have a comprehensive system model supporting multiple components at the same time. We propose a new method for modeling and selecting the power modes for the optimal system-power management of embedded systems under timing and power constraints. First, we not only model the modes and the transitions overhead at the component level, but we also capture the application-imposed relationships among the components by introducing a mode dependency graph at the system level. Second, we propose a mode selection technique, which determines when and how to change mode in these components such that the whole system can meet all power and timing constraints. Our constraint-driven approach is a critical feature for exploring power/performance tradeoffs in power-aware embedded systems. We demonstrate the application of our techniques to a low-power sensor and an autonomous rover example.

Efficient Generation of Delay Change Curves for Noise-Aware Static Timing Analysis

Abstract: In this paper, we explore the concept of using analytical models to efficiently generate delay change curves (DCCs) that can then be used to characterize the impact of noise on any victim/aggressor configuration. Such an approach captures important noise considerations such as the possibility of delay change even when the switching windows of neighboring gates do not overlap. The technique is model-independent, which we demonstrate by using several crosstalk noise models to obtain results. Furthermore, we extend an existing noise model to more accurately handle multiple aggressors in the timing analysis framework. DCC results from the analytical approach closely match those from time-consuming SPICE simulations, making timing analysis using DCCs efficient as well as accurate.

Topological Analysis for Leakage Prediction of Digital Circuits

Abstract: Subthreshold leakage current is becoming an increasingly significant portion of the power dissipation in microprocessors due to technology and voltage scaling. Techniques to estimate leakage at the full chip level are indispensable for power budget allocation. In addition, simple and practical approaches and rules of thumb are needed to allow leakage to become part of the vocabulary of all designers. This paper focuses on the impact of circuit topology on leakage, which is often abstracted through what is referred to as the stacking factor. The stacking factor which captures the leakage reduction in series connected devices, is a first order term in leakage estimation equations and has significant impact on estimation results. The authors present two analysis methods, one mathematical and one empirical, to identify the stacking factor for leakage prediction. Understanding the stacking factor as well as obtaining an accurate estimate of its value, is critical in reducing prediction uncertainty. As leakage prediction becomes a bigger factor in roadmap decisions, reducing leakage prediction uncertainty will be key in accurate determination of product specifications.

Multiple Faults: Modeling, Simulation and Test

Abstract: We give an algorithm to model any given multiple stuck-at fault as a single stuck-at fault. The procedure requires insertion of at most n+3 modeling gates, when the multiplicity of the targeted fault is n. We prove that the modeled circuit is functionally equivalent to the original circuit and the targeted multiple fault is equivalent to the modeled single stuck-at fault. The technique allows simulation and test generation for any arbitrary multiple fault in combinational or sequential circuits. We further demonstrate applications to bridging fault modeling, diagnosis, circuit optimization, and testing of multiply-testable faults. The modeling technique has an additional application in a recently published combinational ATPG method for partial-scan circuits in which some lines are split, leading to a transformation of single stuck-at faults into multiple faults.

Dynamic noise analysis with capacitive and inductive coupling [high-speed circuits]

Abstract: In this paper we propose a dynamic noise model to verify functional failures due to crosstalk in high-speed circuits. Conventional DC noise analysis produces pessimistic results because it ignores the fact that a gate acts as a low-pass filter. In contrast, the dynamic noise model considers the temporal property of a noise waveform and analyzes its effect on functionality. In this model, both capacitive and inductive coupling are considered as the dominant source of noise in high-speed deep-submicron circuits. It is observed that in the case of the local interconnects (where wire lengths are short), the effect of inductive coupling is small; however for long interconnects this effect may be considerable. Based on this noise model, we have developed an algorithm to verify high-speed circuits for functional failures due to crosstalk. The design of a 4-bit precharge-evaluate full adder circuit is verified, and many nodes which are susceptible to crosstalk noise are identified. It is observed and further verified by SPICE simulation that dynamic noise analysis is more realistic for verifying functional failures due to crosstalk than DC noise analysis.

T3: Trends and Challenges in VLSI Technology Scaling towards 100nm

Abstract: Summary form only given. Moore's Law drives VLSI technology to continuous increases in transistor densities and higher clock frequencies. This tutorial will review the trends in VLSI technology scaling in the last few years and discuss the challenges facing process and circuit engineers in the 100nm generation and beyond. The first focus area is the process technology, including transistor scaling trends and research activities for the 100nm technology node and beyond. The transistor leakage and interconnect RC delays will continue to increase. The tutorial will review new circuit design techniques for emerging process technologies, including dual Vt transistors and silicon-on-insulator. It will also cover circuit and layout techniques to reduce clock distribution skew and jitter, model and reduce transistor leakage and improve the electrical performance of flip-chip packages. Finally, the tutorial will review the test challenges for the 100nm technology node due to increased clock frequency and power consumption (both active and passive) and present several potential solutions.

A Unified Method to Handle Different Kinds of Placement Constraints in Floorplan Design

Abstract: In floorplan design, it is common that a designer will want to control the positions of some modules in final packing for various purposes such as data path alignment, I/O connection, etc.. There are several previous works (Young and Wong, 1998 and 1999; Young et al, 1999; Murata et al, 1997; Chang et al, 2000) focusing on a few particular kinds of placement constraint. In this paper, we present the first "unified method" to handle all of them simultaneously, including pre-placed constraint, range constraint, boundary constraint, alignment, abutment and clustering, etc., in general nonslicing floorplans. We have used incremental updates and an interesting reduced graphs idea to improve the runtime of the algorithm. We tested our method using some benchmark data with about one eighth of the modules having placement constraints and the results are very promising. Good packing with all the constraints satisfied can be obtained efficiently.

Automatic Model Refinement for Fast Architecture Exploration

Abstract: We present a methodology and algorithms for automatic refinement from a given design specification to an architecture model based on decisions in architecture exploration. An architecture model is derived from the specification through a series of well defined steps in our design methodology. Traditional architecture exploration relies on manual refinement which is painfully time consuming and error prone. The automation of the refinement process provides a useful tool to the system designer to quickly evaluate several architectures in the design space and make the optimal choice. Experiments with the tool on a system design example show the robustness and usefulness of the refinement algorithm.

Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire Sizing

Abstract: We describe a new algorithm for floorplan evaluation using timing-driven buffered routing according to a prescribed buffer site map. Specifically, we describe a provably good multi-commodity flow based algorithm that finds a global routing minimizing routing area (wirelength and number of buffers) subject to given constraints on buffer/wire congestion and sink delays. This permits detailed floorplan evaluation, i.e. computing the trade-off curve between routing area and wire/buffer congestion under any combination of delay and capacity constraints. Our algorithm (1) enforces maximum source/buffer wireloads; (2) enforces wire and buffer congestion constraints by taking into account routing channel capacities and buffer site locations; (3) enforces individual sink delay constraints; (4) performs buffer/wire sizing and layer assignment; and (5) integrates pin assignment with virtually no increase in runtime. Preliminary experiments show that near-optimal results are obtained with a practical runtime.

A Parallel and Accelerated Circuit Simulator with Precise Accuracy

Abstract: We have developed a hi ghly parallel and accelerated circuit simulator which produces precise results for large scale simulation. We incorporated multithreading in both the model and matrix calculations to achieve not only a factor of 10 acceleration compared to the defacto standard circuit simulator used worldwide, but also equal or exceed the performance of timing-based event -driven simulators with the accuracy which matches that of SPICE-based circuit simulation. For example, a 89K element DRAM CAS circuit simulation can be performed in under 38 minutes with timing accuracy error as little as 7 ps.

Automatic modeling and validation of pipeline specifications driven by an architecture description language [SoC]

Abstract: Verification is one of the most complex and expensive tasks in the current systems-on-chip (SOC) design process. Many existing approaches employ a bottom-up approach to pipeline validation, where the functionality of an existing pipelined processor is, in essence, reverse-engineered from its RT-level implementation. Our approach leverages the system architect's knowledge about the behavior of the pipelined architecture, through architecture description language (ADL) constructs, and thus allows a powerful top-down approach to pipeline validation. This paper addresses automatic validation of processor, memory, and co-processor pipelines described in an ADL. We present a graph-based modeling of architectures which captures both structure and behavior of the architecture. Based on this model, we present formal approaches for automatic validation of the architecture described in the ADL. We applied our methodology to verify several realistic architectures from different architectural domains to demonstrate the usefulness of our approach.

Timing Yield Calculation Using an Impulse-train Approach

Abstract: This paper presents a new method to compute the probability distribution of the delay of a combinational circuit and uses it to obtain an estimate of the yield of the process that manufactures the circuit. We assume a simple delay model assigning a triangular distribution to the delay of a gate and ignore the logical function of the gate and the pin-to-pin delay. The method can handle tree-like circuits as well as circuits with reconvergent fanout in them. The chief advantage of this method over conventional Monte-Carlo simulation is that it is much faster while providing comparable quality.

Efficient Approximate Balanced Truncation of General Large-Scale RLC Systems via Krylov Methods

Abstract: We present an efficient implementation of an approximate balanced truncation model reduction technique for general large-scale RLC systems, described by a state-space model where the "C" matrix in the time-domain modified nodal analysis (MNA) circuit equation "C\dot{x}=-Gx+Bu" is not necessarily invertible. The large sizes of the models that we consider make most implementations of the balance-and-truncate method impractical from the points of view of computational load and numerical conditioning. This motivates our use of Krylov subspace methods to directly compute approximate low-rank square roots of the Gramians of the original system. The approximate low-order general balanced and truncated model can then be constructed directly from these square roots. We demonstrate using three practical circuit examples that our new approach effectively gives approximate balanced and reduced order coordinates with little truncation error.

Impact of Technology Scaling on Metastability Performance of CMOS Synchronizing Latches

Abstract: In this paper, we use circuit simulations to characterize the effects of technology scaling on the metastability parameters of CMOS latches used as synchronizers. We perform this characterization by obtaining a synchronization error probability curve from a histogram of the latch delay. The main metastability parameters of CMOS latches are /spl tau//sub m/ and T/sub w/. /spl tau//sub m/ is the exponential time constant of the rate of decay of metastability and T/sub w/ is effective metastability window size at a normal propagation delay. Both parameters can be extracted from a histogram of the latch delay. This paper also explains a way to calibrate the simulator for accuracy. The simulations indicate that /spl tau//sub m/ scales better than the technology scale factor. T/sub w/ also scales down but its factor cannot be estimated as well as that of /spl tau//sub m/. This is because T/sub w/ is a complex function of signal and clock edge rate and logic threshold level.

Power Supply Noise Aware Floorplanning and Decoupling Capacitance Placement

Abstract: Power supply noise is a strong function of the switching activities of the circuit modules. Peak power supply noise can be significantly reduced by judiciously arranging the modules based on their spatial correlations in the floorplan. In this paper, power supply noise is, for the first time, incorporated into the cost function to determine the optimal floorplan in terms of area, wire length, and power supply noise. Compared to conventional floorplanning, which only considers area and wire length, power supply noise aware floorplanning can generate better floorplan both in terms of area and peak noise. The decoupling capacitance required by each module is also calculated and placed in the vicinity of the target module during the floorplanning process. Experimental results on MCNC benchmark circuits show that the peak power supply noise can be reduced by as much as 40% and both the total area and wire length are improved due to the reduced total decoupling capacitance budget gained from reduced power supply noise.

Automatic Synthesis of CMOS Operational Amplifiers: A Fuzzy Optimization Approach

Abstract: In this paper, we present a method for optimizing and automating the components and transistor sizing for CMOS operational amplifiers (op-amps). The optimization approaches used for the synthesis of analog circuits are found to be very much rigid in terms of capturing human intentions. In this work, we have observed that with the use of fuzzy membership functions, human intentions for expressing wide variety of requirements, e.g., minimize power, maximize gain, etc., which are often conflicting in nature, can be captured effectively in order to formulate the objective function. For each of the performance specifications of a given topology, a membership function is assigned to measure the degree of fulfillment of the objectives and the constraints. A number of objectives are optimized simultaneously by assigning weights to each of them representing their relative importance, and then by clustering together to form the objective function that is solved by an optimization algorithm. We have considered the channel length modulation parameter for the computation of DC bias point and small signal parameters. The design results obtained from our optimization algorithm showed an excellent match with those obtained from SPICE simulation for a number of op-amp topologies.