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Conference

Asia Symposium on Quality Electronic Design 

About: Asia Symposium on Quality Electronic Design is an academic conference. The conference publishes majorly in the area(s): CMOS & Logic gate. Over the lifetime, 351 publication(s) have been published by the conference receiving 1384 citation(s).
Papers published on a yearly basis
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Proceedings ArticleDOI
Quan Zhou1, Xueyan Wang1, Zhongdong Qi1, Zhuwei Chen1, Qiang Zhou1, Yici Cai1 
24 Sep 2015
TL;DR: Using a well-trained model, most design rule violations after detailed routing can be foreseen in placement stage and the average prediction accuracy is comparable with other state-of-art routability estimation techniques.
Abstract: Routability is one of the primary objectives in placement. There have been many researches on forecasting routing problems and improving routability in placement but no perfect solution is found. Most traditional routability-driven placers aim to improve global routing result, but true routability lies in detailed routing. Predicting detailed routing routability in placement is extremely difficult due to the complexity and uncertainty of routing. In this paper, we propose a new detailed routing routability prediction model based on supervised learning. After extracting key features in placement and detailed routing, multivariate adaptive regression is performed to train the connection between these two stages. Using a well-trained model, most design rule violations after detailed routing can be foreseen in placement stage. Experiments show that our average prediction accuracy is 79.8%, which is comparable with other state-of-art routability estimation techniques.

39 citations


Proceedings ArticleDOI
10 Jul 2012
TL;DR: This paper is presenting efficient algorithm for solar energy prediction based on additive decomposition (SEPAD) model, which is individually considering both seasonal and daily trends along with Sun's diurnal cycle.
Abstract: Recently, wireless sensing nodes are being integrated with ambient energy harvesting capability to overcome limited battery power budget constraint and extending effective operational time of sensor network. Solar panels are more frequently used to collect light energy for wireless sensing node. In order to efficiently utilize solar harvested energy in design, precise solar harvested energy prediction is a challenging task due to irregularity in solar energy patterens because of continually changing weather conditions. In this paper, we are presenting efficient algorithm for solar energy prediction based on additive decomposition (SEPAD) model. In this model, we are individually considering both seasonal and daily trends along with Sun's diurnal cycle. The performance of this algorithm is compared with existing solar energy prediction approaches and results show that our algorithm performance is better than existing approaches.

29 citations


Proceedings ArticleDOI
16 Aug 2010
Abstract: In this paper, the variations of the main characteristics in three SOI device structures due to channel length and thin-film thickness variations are investigated. The structures are studied in a 32nm technology and include SOI-GPS (Ground-Plane in Substrate), SOI-GPB (Ground-Plane in BOX), and SOI-WGP (Without Ground Plane). For this study, we assume normal distributions for the channel length and thin-film thickness of the transistors and then obtain the distributions for the threshold voltage, leakage, DIBL coefficient, and subthreshold swing. The results show that the GPS structure is more resistant against the variations when compared to the other two structures.

29 citations


Proceedings ArticleDOI
24 Sep 2015
TL;DR: This work has achieved the smallest FPGA implementation of the PRESENT cipher to date, requiring only 62 slices on the Virtex-5 XC5VLX50 platform, and features a respectable throughput of 51.32 Mbps at the maximum frequency of 236.574 MHz.
Abstract: Ever since the conception of the ideology known as the Internet of Things (IoT), our world is slowly approaching the brink of mankind's next technological revolution The realization of IoT requires an enormous amount of sensor nodes to acquire inputs from the connected objects Due to the lightweight nature of these sensors, constraints emerge in the form of limited power supply and area for the implementation of information security mechanism To ensure security in the data transmitted by these sensors, lightweight cryptographic solutions are required In this work, our goal is to implement a compact PRESENT cipher onto a Field Programmable Gate Array (FPGA) platform Our proposed design uses an 8-bit datapath to reduce hardware size Instead of a traditional look-up table (LUT) based S-Box, we have implemented a Boolean S-Box through Karnaugh mapping Further factorization is also done to reduce the size of the Boolean S-Box As a result, we have achieved the smallest FPGA implementation of the PRESENT cipher to date, requiring only 62 slices on the Virtex-5 XC5VLX50 platform Our design also features a respectable throughput of 5132 Mbps at the maximum frequency of 236574 MHz

25 citations


Proceedings ArticleDOI
15 Jul 2009
TL;DR: The peak amplitude of the ground bouncing noise is reduced by up to 69.17% with the noise-aware MTCMOS circuits without sacrificing the savings in leakage power consumption as compared to the standard MTCmOS circuits in a 90nm CMOS technology.
Abstract: Ground bouncing noise produced during the sleep to active mode transitions is an important challenge in Multi-Threshold CMOS (MTCMOS) circuits. The effectiveness of different noise-aware MTCMOS circuit techniques to deal with the ground bouncing noise phenomenon is evaluated in this paper. An intermediate relaxation mode is investigated to gradually dump the charge stored on the virtual ground line to the real ground distribution network during the sleep to active mode transitions. The peak amplitude of the ground bouncing noise is reduced by up to 69.17% with the noise-aware MTCMOS circuits without sacrificing the savings in leakage power consumption as compared to the standard MTCMOS circuits in a 90nm CMOS technology.

23 citations


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Performance
Metrics
No. of papers from the Conference in previous years
YearPapers
201538
201358
201254
201154
201068
200979