Showing papers presented at "Asia Symposium on Quality Electronic Design in 2010"

Process variation study of Ground Plane SOI MOSFET

Abstract: In this paper, the variations of the main characteristics in three SOI device structures due to channel length and thin-film thickness variations are investigated. The structures are studied in a 32nm technology and include SOI-GPS (Ground-Plane in Substrate), SOI-GPB (Ground-Plane in BOX), and SOI-WGP (Without Ground Plane). For this study, we assume normal distributions for the channel length and thin-film thickness of the transistors and then obtain the distributions for the threshold voltage, leakage, DIBL coefficient, and subthreshold swing. The results show that the GPS structure is more resistant against the variations when compared to the other two structures.

A high throughput low power compact AES S-box implementation using composite field arithmetic and Algebraic Normal Form representation

Abstract: In this work, our aim is to achieve a high throughput compact AES S-box with minimal power consumption. In most VLSI implementations, there exist a definite trade off between hardware performance and its operating requirements. In this work, we propose a novel pipelining arrangement over the compact composite field AES S-box such that both high throughput and low power are optimized. Our S-box outperformed the conventional pipelined AES S-box from three perspectives, (i) the most optimum (compact and short critical path) composite field AES S-box is used, which has different arithmetic properties compared to previous works; (ii) Algebraic Normal Form (ANF) representation is utilized to induce consistent and optimal pipelining arrangement; and (iii) Fine-grain pipelining is applied in the GF (24) multiplier. As such, a higher throughput rate is attained and at the same time the dynamic hazards is mitigated. A high throughput of 3.3Gbps with a low power consumption of 34.98mW and total of 95 LE (Logic Element) composite field AES S-box is reported in this work.

Statistical model for subthreshold current considering process variations

Abstract: In this paper, an analytical technique for modeling the statistical distribution of the sub-threshold leakage variation is presented. The technique focuses on the subthreshold leakage variation induced by the within-die channel length variations. The threshold voltage variations due to the channel length variations are also included in the model. The spatial correlations between the parameters as well as the stacking effects in complex gates are considered in the technique. To assess the accuracy of the technique, we compare the results of the model for basic gates and a 1-bit full adder with those of the Monte-Carlo method. The comparison shows a small error of less than 1% for the mean and 10% for the standard deviation for the technologies considered. The same approach may be applied to other parameter variations including temperature, supply voltage, oxide thickness and threshold voltage.

Crosstalk analysis in Carbon Nanotube interconnects and its impact on gate oxide reliability

Abstract: The work analyses the crosstalk effects in Carbon Nanotube (CNT), and its impact on the gate oxide reliability. Using the existing models of CNT, the circuit parameters for CNT-bundle interconnect are calculated and the equivalent circuit has been developed to perform the crosstalk analysis. The crosstalk induced overshoot/undershoots have been estimated and the impact of the overshoot/undershoots on the gate oxide reliability in terms of failure-in-time (FIT) rate is calculated. A similar analysis is performed for Cu interconnects and comparisons are made with CNT based interconnect results. It has been found that the CNT based interconnect is more suitable in VLSI circuits as far as the gate oxide reliability is concerned.

A case study of Short Term Cell-Flipping technique for mitigating NBTI degradation on cache

Abstract: Negative Bias Temperature Instability (NBTI) is one of the major reliability problems in advanced technologies. NBTI causes threshold voltage shift in a PMOS transistor which is biased to negative voltage. In an SRAM cell, due to NBTI, threshold voltage shifts in the load transistors. The degradation has the impact on Static Noise Margin (SNM), which is a measure of read stability of a 6-T SRAM cell. Because an SRAM cell consists of two inverters, one of the load transistors is always stressed. In order to mitigate NBTI degradation, we proposed Short Term Cell-Flipping technique (STCF) for SRAM cell. This technique makes the stress probability on load transistors in an SRAM cell close to 50%. In this paper, we apply STCF technique to cache memories, and discuss its potential to mitigate NBTI degradation.

Active filters for harmonics elimination in solar photovoltaic grid-connected and stand-alone systems

Abstract: Power converter's output signal harmonic control is currently becoming immensely important in medium and high power applications due to the development of new grid codes. Advancement in transistor technology has lead to significant changes from large thyristor-equipped grid-connected inverters to smaller and fast switching IGBT (Insulated Gate Bipolar Transistors) equipped converters. These IGBT's increases the power switching frequency in order to extract more energy and fulfill the grid connecting standards. Grid codes usually define a maximum allowed level for each specific harmonic and determine the maximum tolerated THD (Total Harmonic Distortion) of the output signals. Unfortunately, these IGBT-based power drivers generate harmonics that are subsequently transmitted into the power bus. The harmonics are normally eliminated by passive LC or RLC filters. However this passive filtering system has its own limitations. In this paper, we analyze the harmonics created by the IGBT-equipped converter using Fast Fourier Transform (FFT) analysis. The converters are connected to the PV (Photovoltaic) arrays and the utility grid for grid-connected applications and PV arrays & battery modules for stand-alone applications. Using a second-order Butterworth Filter we showed that the THD has been reduced from 32.59% to 1.59%.

Block-based compressive sampling for digital pixel sensor array

Abstract: In this paper, a block-based online compressive sampling scheme for digital pixel sensor (DPS) is proposed The overall sensor array is divided into blocks whereby one randomly selected pixel within each block is sampled using a random access control circuit The latter is performed using off-array horizontal and vertical control logic The random access addresses are updated during readout phase using low complexity logic operations performed on the readout pixel values A sparse matrix, consisting of all the sampled pixel values, is buildup to reconstruct the image by solving the l 1 -norm minimization as the linear programming problem in the framework of Convex Optimization The proposed system features reduced on-chip compression processing complexity and significant reduced memory requirement System level simulation results show that a 25dB reconstructed image quality in terms of PSNR is achieved enabling a compression ratio of 4 In addition, a pixel-level memory requirement reduction of 75% is achieved when compared to a standard PWM DPS architecture

FPGA implementation of compressive sampling for sensor network applications

Abstract: This paper examines the implementation considerations of Compressive Sampling (CS) in Field Programmable Gate Array (FPGA) and proposes computation-free linear projection implementation for CS encoding in imaging applications. A simplified sensing matrix is implemented to eliminate the multiplication and summation processes in the sensing stage. This sensing paradigm does not require all pixels in an image to be fully captured before being projected into measurements. This is in contrast with the case when Gaussian or Noiselet sensing matrix is applied. Though the recovered image obtained by this work is 2.64dB lower in PSNR than that of the optimal Gaussian matrix, the problem of Saturation noise caused by significantly increased dynamic range of the measurements compared with the original pixel value could be avoided in the practical applications. This compressive sampling scheme is implemented in FPGA and is interfaced with a CMOS imager for experimental validation.

A new CMOS/microfluidic interface for cells manipulation and separation in LoC devices

Abstract: We propose in this paper a new fully integrated CMOS interface dedicated for cells manipulation and separation in LoC devices. The proposed interface includes all microelectronics circuits for dielectrophoretic manipulation and capacitive detection. It contains also an embedded frequency and phase micro controller to ensure several kinds of cells displacements such as rotation, translation and separation with a wide tunable frequency band of 250 kHz for LoC applications. Furthermore, the detection part is a charge-based capacitive measurement circuit with a high sensitivity of 10 mV for each 1 fF. This new chip is a fully integrated CMOS interface into a LoC device including both the microfluidic and the microelectronics structures. It represents one of the first microfluidic processors.

Hardware computing for brain network analysis

Abstract: As the scale of computer clusters and supercomputers is getting larger, the problem of power consumption and heat dissipation has become the biggest obstacle for the ever growing need for computation. Designing platforms for specific applications using the reconfigurable logic such as Field Programmable Gate Arrays (FPGAs) or highly parallel processors such as Graphic Processing Units (GPUs) will dramatically increase power efficiency. This is the concept of domain specific computing. Combining the advantages of different platforms to build a heterogeneous computing platform is the trend of domain specific computing. On the other hand, the research on brain networks plays a vital role in understanding the connectivity patterns of the human brain and disease-related alterations. Recent studies have suggested a noninvasive way of modeling and analyzing the human cortical networks with MRI by graph theory based approaches. However, both the construction and analysis of brain networks require tremendous computation. Currently, only hundreds of nodes can be analyzed due to lack of computing power. By increasing the number of nodes, the resolution of cortical networks will be greatly enhanced, thus hopefully helps the early diagnosis of brain diseases such as Alzheimer's disease. A well-designed computing platform is the key to this problem. In this work, we inject the power of heterogeneous hardware computing into the brain network research, to help the research on the connectivity patterns of both normal and diseased brains. Besides, one important outcome is an accelerated BLAS and Graph algorithms package, which will provide insights into domain specific computing to boarder audience in both biomedical and computer science domains.

Extended compatibility path based hardware binding algorithm for area-time efficient designs

Abstract: Hardware binding is a crucial step in high-level synthesis. In this paper we propose a path based hardware binding algorithm to create area-time efficient designs. The algorithm performs simultaneous FU and register binding based on weighted and ordered compatibility graphs. The proposed algorithm tries to reduce interconnects in the design by exploiting flow dependencies in the DFG, leading to area reduction. The algorithm has been successfully implemented within a C to RTL framework. Experimental results on a set of commonly used benchmarks show that the proposed algorithm is able to achieve significant reductions in routing resources, area and delay when compared to the weighted bipartite matching(WBM) algorithm and the compatibility path based(CPB) binding method. In addition, when compared to WBM and CPB methods, the new algorithm has an average reduction of 29.21% & 12.49% in the area-time product respectively.

Derivative superposition method for DG MOSFET application to RF mixer

Abstract: A high linear double-gate (DG) MOSFET application to RF mixer is proposed based on derivative superposition method which was successfully used in Bulk CMOS region. By independently biasing front and back gate voltage of DG MOSFET, one DG MOSFET device is reviewed as two parallel devices. In this way, we realize the derivative superposition method application in the DG MOSFET linearity analysis and high performance RF mixer. Via two-dimensional (2D) TCAD device simulation and through the third-order transconductance (gm3) cancellation, we get some interesting results of DG MOSFET mixer different from the Bulk CMOS mixer. It is found that the DG MOSFET is suitable to work as a single device mixer because of coupling effect of two gates, e.g., a high linear independent DG MOSFET mixer shows 7.8dB improvement on IIP3 corresponding to the symmetrical DG mixer with the same DC current. The relationships between the amplitude of LO signal, the conversion gain and linearity are also analyzed in this paper.

A toggle-type peak hold circuit for local power supply noise detection

Abstract: In this paper, a new peak hold circuit which detects the top value and the bottom value of the power supply noise of a VLSI circuit is proposed. We can make a noise map by distributing the circuit over the chip and find hot-spots in which large power supply noise occurs. This circuit needs no extra clean power supply or external clock signal. Also, low power consumption can be expected because it is composed simple and small. Our circuit can hold both the top peak value and bottom peak value by changing only one gate logic. Moreover, our circuit has a mechanism of DC offset cancellation. This circuit has a resolution of 10mV at 100MHz. The output value from two or more circuits can be transmitted via a shared single wire. HSPICE simulation using a 0.18µm CMOS process technology validates its operation.

A high-throughput, metastability-free GALS channel based on pausible clock method

Abstract: Synchronization issues such as metastability in multi-clock domain systems have become a big problem, reducing data transmission throughput between domains In this paper, a high-throughput, metastability-free data transmission channel based on pausible clock method in Globally-Asynchronous Locally-Synchronous (GALS) systems is proposed This channel can be used as the interconnection of mixed-clock synchronous IP cores without having concerns about their synchronization We show that the probability of metastability in our design is practically zero; and this without loss of throughput and latency, allowing the transmitter and receiver to operate with their own maximum clock frequency The proposed channel is simulated in 90nm CMOS process using Predictive Technology Model (PTM) library Gate delays and power parameters are extracted from Spice simulations and are back annotated into our channel HDL code The throughput, latency and power are analyzed and compared with existing designs

The impact of electromagnetic coupling of guard ring metal lines on the performance of On-chip spiral inductor in silicon CMOS

Abstract: The grounded metal guard rings are useful in isolating the coupling of inductors to other on-chip inductors as well as other components. These guard rings influence the performance of the inductor itself. This paper investigates and analyzes the electromagnetic (EM) coupling of the guard ring to the inductor and investigates its impacts on its performance parameters such as the quality-factor (Q) and effective inductance (L eff ). Three inductor test structures surrounded by a grounded metal guard ring with spacing 30µm, 50µm and 80µm from inductor have been fabricated using Silterra CMOS 0.13µm process. Measurement results show that maximum Q (Q max ) degradation can be around 30% compared to the case of inductor without grounded metal guard ring. The measured results are analyzed with the help of EM simulation using Cadence's Virtuoso Passive Component Designer (VPCD) simulator. The performance degradation curves as a function of guard ring spacing to inductor are reported.

Characterizing PLL Jitter from power supply fluctuation using mixed-signal simulations

Abstract: Characterizing PLL Jitter is important yet challenging. Usually done through transistor-level transient analysis, slow simulation speed has been the major bottleneck preventing jitter from being characterized in a timely manner. This paper presents an approach for fast jitter characterization using mixed-signal simulation (combination of transistor-level blocks and calibrated behavioral models). Among various PLL jitter mechanisms, jitter from CMOS gate switching threshold variation due to power supply fluctuation is chosen to be the focus. Analog/digital converters carrying dynamic power supply dependency, together with behavioral models written in Verilog-AMS, are used to approximately model and characterize the targeted type of jitter. Jitter characterization using this method is applied to two PLL blocks, phase detector and frequency divider. Results show that jitter measured from the proposed method is in good agreement with transistor-level simulation and the speed improvement from mixed-signal simulation is significant, proving this method to be a feasible approach for fast jitter characterization.

Optimizing device size for soft error resilience in sub-micron logic circuits

Abstract: As technology nodes are being scaled down, soft errors induced by particle strikes are becoming a troublesome reliability issue in logic circuits. Various sizing techniques commonly used to reduce soft error rate in the past are expensive in terms of area, performance, and energy consumption. These methods require changes to adapt to sub-micron technologies. This study introduces two novel sizing methods that selectively upsize transistor networks of a circuit. Our first proposed methodology formulates the soft error rate minimization as a mathematical optimization problem and searches for the best area distribution such that maximum reliability gain is obtained. This methodology assures that optimal solutions are achieved within given area budget provided to the designer. However, generating optimal solution requires very high CPU time. Therefore, we propose a heuristic based methodology which upsizes only selected transistor network in sensitive gates based on soft error sensitivity of each gate. With proper sensitive gate selection and area distribution algorithms proposed in this technique, we show through experimental results that our heuristic driven method gives satisfactory reliability improvement compared to our first method, while requiring relatively small computation time.

Power density aware power gate placement optimization scheme

Abstract: As we are marching towards deeper sub-micron technology from process scaling, the transistor leakage itself had became more and more dominant to the total component power, which is unavoidable. Clever employment of power gating / sleep transistor / MTCMOS technology can help to shut off leakage power from un-use blocks. However over placement of power gate cells to reduce ON stage IR voltage drop can yield higher leakage power during OFF stage at high temperature and fast skew. This paper described the circuit analysis, optimization strategies and design methodology to tackle this issue head on. A proposal on power gate placement optimization using the concept of power windowing and Power Perimeter Scan (PPS) was introduced in this paper. Details break down of circuit modeling and design trade off on Power Gating FETs was described including simulation results and equations to aid the illustrations. The overall power saving using MTCMOS was re-evaluated for total leakage minimization.

A novel VLSI architecture for Walsh-Hadamard transform

Abstract: In this paper, a novel VLSI architecture for one dimensional Walsh-Hadamard transform (WHT) is proposed. The core of the architecture is the HVMA (Hadamard Vector Merging Adder) that adds the products of input data words and transform (Hadamard) matrix elements in parallel using a (4:2) compressor based carry-save tree structure. The core also exploits the Hadamard matrix's property of equal distribution of +1 and −1 in all rows and columns, except for the first row and the first column. The VLSI implementation of the architecture for transforming an (8×8) image block using Field Programmable Gate Array (FPGA) results in clock frequency of 101 MHz, and power consumption of 424 mW. The energy consumption, calculated as power-latency product, is 678.4 nJ, which is 20.6% lower than the existing architecture with the minimum value reported in the literature. The throughput for a (8×8) block is 633.66ns which is 46.9% lower than the fastest architecture.

The application of spintronic devices in magnetic bio-sensing

Abstract: Recently integrated magnetic/spintronic device microarrays have demonstrated great potentials in both biomedical research and practices. In this work, we discuss the physical mechanisms of three types of spintronic devices for magnetic signal sensing, including giant magnetoresistance (GMR) spin valve sensors, tunnel magnetoresistance (TMR) sensors and our newly proposed spintronic memristor sensors. The DNA hybridization detection with magnetic nanoparticle labels is used as the case study to depict the corresponding magnetic and circuit design tradeoffs for different spintronic devices.

A complementary single-electron 4-bit multiplexer

Abstract: The design and simulation of a single-electron 4-1 complementary multiplexer is being presented using two Monte Carlo based tools. Both the behavior and the stability of the circuit were verified while its free energy and its speed were also examined and analyzed. The results confirmed that the circuit behaved as a complementary multiplexer. Moreover, the currents through the circuit were examined under the operating temperature, while a stable operation of the circuit was verified without any noise present at the output points.

A nonlinear S-parameters behavioral model for RF LNAs

Abstract: A nonlinear behavioral model for radio frequency low noise amplifiers (LNA's) is presented. The model captures effects of nonlinearity, output power saturation, noise figure and port impedance mismatch. A high-level S-parameters approach is adopted during the model derivation. Consequently, the model inherits the S-parameters dual ability to characterize the transfer function between ports while including their impedances. The model derivation is thoroughly discussed showing how the effects of intermodulation as well as output power saturation can be included within the S-parameters representation for the block. Furthermore, in order to minimize the calibration effort, the model generics are made such that they map directly to typical LNA specifications. It follows that the model as implemented is not topology specific and can be easily calibrated to serve within top-down or bottom-up verification flows. Finally, the model accuracy is validated against reference transistor level simulations. Results comparison shows good agreement is attained.

High-speed and low-leakage MTCMOS memory registers

Abstract: Various high speed sequential multi-threshold voltage CMOS (MTCMOS) circuit techniques are presented and evaluated in this paper. Dedicated low leakage data preserving memory elements are integrated into the MTCMOS flip-flops. The leakage power consumption of an MTCMOS memory register is reduced by up to 67.72% as compared to the previously published conventional sequential MTCMOS circuits in a UMC 80nm CMOS technology. The control scheme required to implement a low leakage sleep mode is significantly simplified with the memory register. Furthermore, the area of the memory register is reduced by up to 46.43% as compared to the conventional MTCMOS registers.

Thermal analysis of high power LEDs at different drive-in current

Abstract: This paper focuses on the thermal characterization of high power white light LED of 1W and 3W. Thermal transient method is used to measure the junction temperature and calculate the thermal resistance. The emphasis is placed upon the investigation of junction temperature in both the 1W and 3W LEDs for a limited range of drive-in current (500mA up to 1A) with the air velocity kept constant throughout the experiment. All investigations are based on the transient junction temperature measurements performed during the cooling process. The presented results include the cumulative structure functions and differential structure functions. It was found that the measured junction temperatures and thermal capacitances of both the LEDs increased with the input power (drive-in current). However, the thermal resistance decreased with the increase of drivein current.

Design aware scheduling of dynamic testbench controlled design element accesses in FPGA-based HW/SW co-simulation systems for fast functional verification

Abstract: In HW/SW co-simulation based logic verification systems [1, 2], the design under test (DUT) is executed on an FPGA based emulator and the behavioral testbench written in some high level language like C or HDL is run on a SW simulator or a general purpose CPU. In such systems it is essential to reduce the communication between SW and HW sides to enhance overall verification speed. Therefore it is of significant importance to efficiently schedule testbench controlled accesses to design elements like flip-flops, memories etc, which require access to FPGA HW. Such accesses by static HDL testbenches which are specified at design compilation time and are mainly to design IOs are optimized by synthesis of RTL transactors [6, 7, 8, 9], which make use of specialized high speed links and standardized interfaces like SCE-MI [13] for optimizing the transactions. It is seen that apart from static testbenches, verification engineers and designers often make use of dynamic random access to design elements (e.g a series of register sets) through C or TCL based dynamic testbenches typically specified post design compilation. Such dynamic accesses are not routed through the transaction link and follow a fixed cost scheduling, resulting in sub-optimal communication pattern between SW and HW verification engines. The paper presents a design aware scheduling system for optimizing such dynamic accesses, by extracting and making use of design characteristics for intelligently clubbing and scheduling various read/write accesses while maintaining modeling fidelity. This complements the streaming transaction based interfaces available for static accesses. It is seen that when this scheduling system is implemented in an industry standard FPGA based co-simulator, evaluation fidelity is maintained and significant enhancement in overall functional verification performance is achieved.

A low-noise phase-locked loop with programmable gain VCO

Abstract: In this paper, a phase-locked loop (PLL) with programmable gain VCO is proposed and analyzed. The proposed design adjusts the gain of the VCO based on the input frequency and the charge pump and loop filter settings in order to achieve lower phase noise. The proposed design is implemented using TSMC 45nm CMOS with a 0.9-V supply voltage. The pre-layout simulation shows that the random jitter of the system is improved when the VCO gain is reduced.

A 1.2-V reconfigurable resolution CMOS image sensor with energy harvesting capability

Abstract: In this paper, we propose a low voltage, low power, reconfigurable resolution CMOS image sensor with energy harvesting capability for wireless image sensor networks. Logarithmic type pixel is adopted to provide a wide dynamic range for image capturing. Semi-pixel level single slope analog-to-digital conversion is realized by employing in-pixel transistors as a part of the column comparator. A correlated double sampling (CDS) control transistor is introduced to remove fixed pattern noise (FPN) due to transistor threshold voltage variations. Energy/power scalability is achieved through reconfiguring the spatial resolution of the imager. The photodiode in the proposed pixel can be used as an energy harvesting device to scavenge energy from the ambient light after photo-sensing. The proposed 64 × 66 imager is designed with AMIS CMOS 0.35-µm digital process, and operates at a supply voltage of 1.2V. It can achieve a dynamic range of 108.6dB with an energy efficiency of 10.74nJ/pixel/frame in simulation. A comparison with other reported designs reveals that the proposed imager is one of the most energy efficient imagers of wide dynamic range. Moreover, the energy harvesting capability of the proposed imager could lead to further improved energy efficiency.

The influence of still air environment on thermal transient measurement of high power LED

Abstract: The surrounding air influence on the thermal transient measurement was studied. The measurements were carried out by setting two boundary conditions where one was measured in open air condition and another transient was captured under still air environment. The data obtained were analysed using structure function evaluation. Analysis of the experimental methods reveal that the thermal resistance of the high power LED is much lower in still air condition compared to open air condition. For the same driving current of 600mA, the total thermal resistance for open air was 8.07692K/W whereas as for still air condition the value was much lower, 7.26577K/W.

Dynamic forward body bias enhanced tri-mode MTCMOS

Abstract: Ground bouncing noise produced during reactivation events is an exacerbating challenge to maintain accurate logic levels in Multi-threshold CMOS (MTCMOS) circuits. A new noise-aware MTCMOS circuit with dynamic forward body bias is explored in this paper to minimize the ground bouncing noise with smaller sleep transistors. The dynamic-forward-body-biased MTCMOS circuit lowers the peak ground bouncing noise by up to 27.76% while reducing the size of the additional sleep transistor by 85.71% as compared to the previously published noise-aware MTCMOS techniques with standard zero-body-biased high threshold voltage sleep transistors. Furthermore, the proposed forward body bias circuit technique achieves up to 14.67% noise reduction and 70% sleep transistor downsizing as compared to a previously published forward-body-biased tri-mode MTCMOS circuit technique. The design tradeoffs between ground bouncing noise and leakage power consumption are evaluated for various MTCMOS circuits in a UMC 80nm CMOS technology.

Wirebond Vs. flip chip design of high speed 3D stacked memory packages

Abstract: 3D Memory package-on-package stacking has gained popularity due to increase in demand for bandwidth, higher density and miniaturization. Challenges in design of high performance 3D stacks have increased with amplification in speed and signal integrity issues. This paper dissects the design elements of 3D memory stacks architecture and characterizes the signal integrity and trade off of wirebond and flip-chip stacks for high data rate applications. Signal integrity characterization of up to 10 stacked packages in both wirebond and flip chip configurations are presented. Effect of BGA stacking, transmission line and wirebond vs flip chip design in both time and frequency domains are analyzed and presented.